Datasheet

520
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
3. Write PIO_PCMR to set the PCEN bit to 1 in order to enable the parallel capture mode WITHOUT changing the
previous configuration.
4. Wait for a data ready by polling the DRDY flag in PIO_PCISR (“PIO Parallel Capture Interrupt Status Register” ) or
by waiting the corresponding interrupt.
5. Check OVRE flag in PIO_PCISR.
6. Read the data in PIO_PCRHR (“PIO Parallel Capture Reception Holding Register” ).
7. If new data are expected go to step 4.
8. Write PIO_PCMR to set the PCEN bit to 0 in order to disable the parallel capture mode WITHOUT changing the
previous configuration.
With PDC
1. Write PIO_PCIDR and PIO_PCIER (“PIO Parallel Capture Interrupt Disable Register” and “PIO Parallel Capture
Interrupt Enable Register” ) in order to configure the parallel capture mode interrupt mask.
2. Configure PDC transfer in PDC registers.
3. Write PIO_PCMR (“PIO Parallel Capture Mode Register” ) to set the fields DSIZE, ALWYS, HALFS and FRSTS in
order to configure the parallel capture mode WITHOUT enabling the parallel capture mode.
4. Write PIO_PCMR to set PCEN bit to 1 in order to enable the parallel capture mode WITHOUT changing the previ-
ous configuration.
5. Wait for end of transfer by waiting the interrupt corresponding the flag ENDRX in PIO_PCISR (“PIO Parallel Cap-
ture Interrupt Status Register” ).
6. Check OVRE flag in PIO_PCISR.
7. If a new buffer transfer is expected go to step 5.
8. Write PIO_PCMR to set the PCEN bit to 0 in order to disable the parallel capture mode WITHOUT changing the
previous configuration.
30.5.14 Write Protection Registers
To prevent any single software error that may corrupt PIO behavior, certain address spaces can be write-protected by
setting the WPEN bit in the “PIO Write Protect Mode Register” (PIO_WPMR).
If a write access to the protected registers is detected, then the WPVS flag in the PIO Write Protect Status Register
(PIO_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
The WPVS flag is reset by writing the PIO Write Protect Mode Register (PIO_WPMR) with the appropriate access key,
WPKEY.
The protected registers are:
 “PIO Enable Register” on page 525
 “PIO Disable Register” on page 525
 “PIO Output Enable Register” on page 526
 “PIO Output Disable Register” on page 527
 “PIO Input Filter Enable Register” on page 528
 “PIO Input Filter Disable Register” on page 528
 “PIO Multi-driver Enable Register” on page 533
 “PIO Multi-driver Disable Register” on page 534
 “PIO Pull Up Disable Register” on page 535
 “PIO Pull Up Enable Register” on page 535
 “PIO Peripheral ABCD Select Register 1” on page 537
 “PIO Peripheral ABCD Select Register 2” on page 538
 “PIO Output Write Enable Register” on page 543
 “PIO Output Write Disable Register” on page 543