Datasheet

407
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
26.10.3.2Slow Clock Mode Transition
A Reload Configuration Wait State is also inserted when the Slow Clock Mode is entered or exited, after the end of the
current transfer (see “Slow Clock Mode” on page 418).
26.10.4 Read to Write Wait State
Due to an internal mechanism, a wait cycle is always inserted between consecutive read and write SMC accesses.
This wait cycle is referred to as a read to write wait state in this document.
This wait cycle is applied in addition to chip select and reload user configuration wait states when they are to be inserted.
See Figure 26-13 on page 404.