Datasheet

148
42023GS–SAM–03/2014
ATSAM4L8/L4/L2
Figure 9-16. SPI Slave Mode, NPCS Timing
Note: 1. These values are based on simulation. These values are not covered by test limits in production.
Maximum SPI Frequency, Slave Input Mode
The maximum SPI slave input frequency is given by the following formula:
Where is the MOSI setup and hold time, SPI7 + SPI8 or SPI10 + SPI11 depending on
CPOL and NCPHA. is the maximum frequency of the CLK_SPI. Refer to the SPI chap-
ter for a description of this clock.
Maximum SPI Frequency, Slave Output Mode
The maximum SPI slave output frequency is given by the following formula:
SPI14
SPI12
SPI15
SPI13
NPCS
SPCK, CPOL=0
SPCK, CPOL=1
Table 9-63. SPI Timing, Slave Mode
(1)
Symbol Parameter Conditions Min Max Units
SPI6 SPCK falling to MISO delay
V
VDDIO
from
2.85V to 3.6V,
maximum
external
capacitor =
40pF
19 47
ns
SPI7 MOSI setup time before SPCK rises 0
SPI8 MOSI hold time after SPCK rises 5.4
SPI9 SPCK rising to MISO delay 19 46
SPI10 MOSI setup time before SPCK falls 0
SPI11 MOSI hold time after SPCK falls 5.3
SPI12 NPCS setup time before SPCK rises 4
SPI13 NPCS hold time after SPCK falls 2.5
SPI14 NPCS setup time before SPCK falls 6
SPI15 NPCS hold time after SPCK rises 1.1
f
SPCKMAX
MIN f
CLKSPI
1
SPIn
------------(,)=
SPIn
f
CLKSPI
f
SPCKMAX
MIN f
PINMAX
1
SPIn t
SETUP
+
------------------------------------(, )=