Datasheet

68
42023GS–SAM–03/2014
ATSAM4L8/L4/L2
8.7.3 Block Diagram
Figure 8-3. Enhanced Debug Port Block Diagram
8.7.4 I/O Lines Description
TCK
RESET_N
TDO
TDI
TMS
boundary_scan
JTAG-FILTER EDP Core reset request
ENHANCED DEBUG PORT
DAP Bus
SW-DP
SWJ-DP
JTAG-DP
BSCAN-TAP
traceswo
swclk
swdio
tdo
tck
tms
tdi
tdo
tck
tms
tdi
tck
reset_n
test_tap_sel
Table 8-1. I/O Lines Description
Name JTAG Debug Port SWD Debug Port
Type Description Type Description
TCK/SWCLK I Debug Clock I Serial Wire Clock
TDI I Debug Data in - NA
TDO/TRACESWO O Debug Data Out O Trace asynchronous Data Out
TMS/SWDIO I Debug Mode Select I/O Serial Wire Input/Output
RESET_N I Reset I Reset