Datasheet

64
42023GS–SAM–03/2014
ATSAM4L8/L4/L2
8.5 Product dependencies
8.5.1 I/O Lines
Refer to Section 1.1.5.1 ”I/O Lines” on page 5.
8.5.2 Power management
Refer to Section 1.1.5.2 ”Power Management” on page 5.
8.5.3 Clocks
Refer to Section 1.1.5.3 ”Clocks” on page 5.
8.6 Core debug
Figure 8-2 shows the Debug Architecture used in the SAM4L. The Cortex-M4 embeds four func-
tional units for debug:
• FPB (Flash Patch Breakpoint)
• DWT (Data Watchpoint and Trace)
• ITM (Instrumentation Trace Macrocell)
• TPIU (Trace Port Interface Unit)
The debug architecture information that follows is mainly dedicated to developers of SWJ-DP
Emulators/Probes and debugging tool vendors for Cortex-M4 based microcontrollers. For further
details on SWJ-DP see the Cortex-M4 technical reference manual.
Figure 8-2. Debug Architecture
8.6.1 FPB (Flash Patch Breakpoint)
The FPB:
• Implements hardware breakpoints
• Patches (on the fly) code and data being fetched by the Cortex-M4 core from code space
with data in the system space. Definition of code and system spaces can be found in the
System Address Map section of the ARMv7-M Architecture Reference Manual.
4 watchpoints
PC sampler
data address sampler
data sampler
interrupt trace
CPU statistics
DWT
6 breakpoints
FPB
software trace
32 channels
time stamping
ITM
SWD/JTAG
SWJ-DP
SWO trace
TPIU