Datasheet

63
42023GS–SAM–03/2014
ATSAM4L8/L4/L2
8.3 Block diagram
Figure 8-1. Debug and Test Block Diagram
note:
Boxes with a plain corner are SAM4L specific.
8.4 I/O Lines Description
Refer to Section 1.1.4 ”I/O Lines Description” on page 4.
SWJ-DP
AHB-AP
TCK
RESET_N
RESET
CONTROLLER
BSCAN-TAP
TDO
TDI
TMS
POR
Boundary
scan
SMAP Core reset request
SMAP
ENHANCED
DEBUG PORT
DAP Bus
Hot_plugging
JTAG-FILTER
AHB
CORTEX-M4
NVICFPB DWT ITM
Core
Instr Data
Private peripheral Bus (PPB)
TPIU
PORT
MUXING
HTOP
APB
AHB
Cortex-M4 Core reset
AHB
M
M
S
Chip Erase
EDP Core reset request
System Bus Matrix