Datasheet

152
42023GS–SAM–03/2014
ATSAM4L8/L4/L2
Note: 1. These values are based on simulation. These values are not covered by test limits in production or characterization.
Table 9-66. SWD Timings
(1)
Symbol Parameter Conditions Min Max Units
Thigh SWDCLK High period
V
VDDIO
from
3.0V to 3.6V,
maximum
external
capacitor =
40pF
10 500 000
ns
Tlow SWDCLK Low period 10 500 000
Tos SWDIO output skew to falling edge SWDCLK -5 5
Tis Input Setup time required between SWDIO 4 -
Tih
Input Hold time required between SWDIO and
rising edge SWDCLK
1-