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ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TQFP 64 (10x10) 32-Bit 48 MHz I/O number 48

Summary

Atmel's SAM4L series is a member of a family of Flash microcontrollers based

on the high performance 32-bit ARM Cortex-M4 RISC processor running at fre-

quencies up to 48MHz.

The SAM4L series embeds state-of-the-art picoPower technology for ultra-low

power consumption. Combined power control techniques are used to bring

active current consumption down to 90µA/MHz. The device allows a wide range

of options between functionality and power consumption, giving the user the

ability to reach the lowest possible power consumption with the feature set

required for the application. The WAIT and RETENTION modes provide full logic

and RAM retention, associated with fast wake-up capability (<1.5µs) and a very

low consumption of, respectively, 3 µA and 1.5 µA. In addition, WAIT mode sup-

ports SleepWalking features. In BACKUP mode, CPU, peripherals and RAM are

powered off and, while consuming less than 0.9µA with external interrupt wake-

up supported.

The SAM4L series offers a wide range of peripherals such as segment LCD con-

troller, embedded hardware capacitive touch (QTouch), USB device & embedded

host, 128-bit AES and audio interfaces in addition to high speed serial peripher-

als such as USART, SPI and I

C. Additionally the Peripheral Event System and

SleepWalking allows the peripherals to communicate directly with each other

and make intelligent decisions and decide to wake-up the system on a qualified

events on a peripheral level; such as I

C address match or and ADC threshold.

Features

• Core

– ARM

Cortex

-M4 running at up to 48MHz

– Memory Protection Unit (MPU)

–Thumb

-2 instruction set

• picoPower

Technology for Ultra-low Power Consumption

– Active mode downto 90µA/MHz with configurable voltage scaling

– High performance and efficiency: 28 coremark/mA

– Wait mode downto 3µA with fast wake-up time (<1.5µs) supporting SleepWalking

– Full RAM and Logic Retention mode downto 1.5µA with fast wake-up time (<1.5µs)

– Ultra low power Backup mode with/without RTC downto 1,5/0.9µA

• Memories

– From 128 to 512Kbytes embedded Flash, 64-bit wide access,

• 0 wait-state capability up to 24MHz

– up to 64Kbytes embedded SRAM

• System Functions

– Embedded voltage linear and switching regulator for single supply operation

– Two Power-on-Reset and Two Brown-out Detectors (BOD)

– Quartz or ceramic resonator oscillators: 0.6 to 30MHz main power with Failure

Detection and low power 32.768 kHz for RTC or device clock

– High precision 4/8/12MHz factory trimmed internal RC oscillator

– Slow Clock Internal RC oscillator as permanent low-power mode device clock

– High speed 80MHz internal RC oscillator

– Low power 32kHz internal RC oscillator

– PLL up to 240MHz for device clock and for USB

42023GS–03/2014

ATSAM---e

ARM-based

Flash MCU

SAM4L Series

Summary

Summary of content (176 pages)

PAGE 1
Summary Atmel's SAM4L series is a member of a family of Flash microcontrollers based on the high performance 32-bit ARM Cortex-M4 RISC processor running at frequencies up to 48MHz. The SAM4L series embeds state-of-the-art picoPower technology for ultra-low power consumption. Combined power control techniques are used to bring active current consumption down to 90µA/MHz.
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ATSAM4L8/L4/L2 • • • • – Digital Frequency Locked Loop (DFLL) with wide input range – Up to 16 peripheral DMA (PDCA) channels Peripherals – USB 2.0 Device and Embedded Host: 12 Mbps, up to 8 bidirectional Endpoints and Multi-packet Ping-pong Mode.
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ATSAM4L8/L4/L2 1. Description Atmel's SAM4L series is a member of a family of Flash microcontrollers based on the high performance 32-bit ARM Cortex-M4 RISC processor running at frequencies up to 48MHz. The processor implements a Memory Protection Unit (MPU) and a fast and flexible interrupt controller for supporting modern and real-time operating systems. The ATSAM4L8/L4/L2 embeds state-of-the-art picoPower technology for ultra-low power consumption.
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ATSAM4L8/L4/L2 events, even in sleep modes where the module clock is stopped. Power monitoring is supported by on-chip Power-on Reset (POR18, POR33), Brown-out Detectors (BOD18, BOD33). The device features several oscillators, such as Phase Locked Loop (PLL), Digital Frequency Locked Loop (DFLL), Oscillator 0 (OSC0), Internal RC 4,8,12MHz oscillator (RCFAST), system RC oscillator (RCSYS), Internal RC 80MHz, Internal 32kHz RC and 32kHz Crystal Oscillator.
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ATSAM4L8/L4/L2 2. Overview 2.1 Block Diagram Figure 2-1.
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ATSAM4L8/L4/L2 2.2 Configuration Summary Table 2-1. Sub Series Summary Feature ATSAM4LC ATSAM4LS SEGMENT LCD Yes No AESA Yes No Device + Host Device Only USB Table 2-2.
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ATSAM4L8/L4/L2 Table 2-2. ATSAM4LC Configuration Summary Feature ATSAM4LC8/4/2C ATSAM4LC8/4/2B ATSAM4LC8/4/2A Digital Frequency Locked Loop 20-150MHz (DFLL) Phase Locked Loop 48-240MHz (PLL) Crystal Oscillator 0.
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ATSAM4L8/L4/L2 Table 2-3. ATSAM4LS Configuration Summary Feature Timer/Counter Channels ATSAM4LS8/4/2C ATSAM4LS8/4/2B 6 3 Parallel Capture Inputs 8 Frequency Meter 1 Watchdog Timer 1 Power Manager 1 Glue Logic LUT Oscillators ADC ATSAM4LS8/4/2A 2 1 Digital Frequency Locked Loop 20-150MHz (DFLL) Phase Locked Loop 48-240MHz (PLL) Crystal Oscillator 0.
PAGE 9
ATSAM4L8/L4/L2 3. Package and Pinout 3.1 Package The device pins are multiplexed with peripheral functions as described in Section 3.2 ”Peripheral Multiplexing on I/O lines” on page 19. 3.1.1 ATSAM4LCx Pinout ATSAM4LC TQFP100 Pinout 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PB11 PB10 PB09 PB08 PC23 PC22 PC21 PC20 PA17 PA16 PA15 PA14 PA13 PC19 PC18 PC17 PC16 PC15 VLCDIN GND BIASL BIASH VLCD CAPL CAPH Figure 3-1.
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ATSAM4L8/L4/L2 Figure 3-2.
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ATSAM4L8/L4/L2 Figure 3-3.
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ATSAM4L8/L4/L2 ATSAM4LC TQFP64/QFN64 Pinout 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PB11 PB10 PB09 PB08 PA17 PA16 PA15 PA14 PA13 VLCDIN GND BIASL BIASH VLCD CAPL CAPH Figure 3-4.
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ATSAM4L8/L4/L2 ATSAM4LC TQFP48/QFN48 Pinout 36 35 34 33 32 31 30 29 28 27 26 25 PA17 PA16 PA15 PA14 PA13 VLCDIN GND BIASL BIASH VLCD CAPL CAPH Figure 3-5.
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ATSAM4L8/L4/L2 3.1.2 ATSAM4LSx Pinout ATSAM4LS TQFP100 Pinout 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PB11 PB10 PB09 PB08 PC23 PC22 PC21 PC20 PA17 PA16 PA15 PA14 PA13 PC19 PC18 PC17 PC16 PC15 PA31 PA30 VDDIO GND PA29 PA28 PA27 Figure 3-6.
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ATSAM4L8/L4/L2 Figure 3-7.
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ATSAM4L8/L4/L2 Figure 3-8.
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ATSAM4L8/L4/L2 ATSAM4LS TQFP64/QFN64 Pinout 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PB11 PB10 PB09 PB08 PA17 PA16 PA15 PA14 PA13 PA31 PA30 VDDIO GND PA29 PA28 PA27 Figure 3-9.
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ATSAM4L8/L4/L2 36 35 34 33 32 31 30 29 28 27 26 25 PA17 PA16 PA15 PA14 PA13 PA31 PA30 VDDIO GND PA29 PA28 PA27 Figure 3-10. ATSAM4LS TQFP48/QFN48 Pinout PA18 PA19 PA20 VDDIO PA21 PA22 PA23 PA24 VDDIO PA25 PA26 GND 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 PA12 PA11 PA10 PA09 PA08 VDDANA ADVREFP GNDANA PA07 PA06 XOUT32 XIN32 12 11 10 9 8 7 6 5 4 3 2 1 PA05 PA04 PA03 TCK VDDIN VDDOUT GND VDDCORE RESET_N PA02 PA01 PA00 See Section 3.
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ATSAM4L8/L4/L2 3.2 Peripheral Multiplexing on I/O lines 3.2.1 Multiplexed Signals Each GPIO line can be assigned to one of the peripheral functions. The following tables (Section 3-1 ”100-pin GPIO Controller Function Multiplexing” on page 19 to Section 3-4 ”48-pin GPIO Controller Function Multiplexing” on page 28) describes the peripheral signals multiplexed to the GPIO lines. Peripheral functions that are not relevant in some parts of the family are grey-shaded.
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ATSAM4L8/L4/L2 Supply Pin ATSAM4LC QFN GPIO 100-pin GPIO Controller Function Multiplexing (Sheet 2 of 4) ATSAM4LS Table 3-1.
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ATSAM4L8/L4/L2 Supply Pin ATSAM4LC QFN GPIO 100-pin GPIO Controller Function Multiplexing (Sheet 3 of 4) ATSAM4LS Table 3-1.
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ATSAM4L8/L4/L2 GPIO Pin ATSAM4LC QFN Supply 100-pin GPIO Controller Function Multiplexing (Sheet 4 of 4) ATSAM4LS Table 3-1.
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ATSAM4L8/L4/L2 Supply GPIO 64-pin GPIO Controller Function Multiplexing (Sheet 2 of 3) Pin ATSAM4LS ATSAM4LC Table 3-2.
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ATSAM4L8/L4/L2 Supply GPIO 64-pin GPIO Controller Function Multiplexing (Sheet 3 of 3) Pin ATSAM4LS ATSAM4LC Table 3-2.
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ATSAM4L8/L4/L2 64-pin GPIO Controller Function Multiplexing for WLCSP package (Sheet 1 of 3) Pin GPIO Supply ATSAM4LS ATSAM4LC Table 3-3.
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ATSAM4L8/L4/L2 Supply Pin GPIO 64-pin GPIO Controller Function Multiplexing for WLCSP package (Sheet 2 of 3) ATSAM4LS ATSAM4LC Table 3-3.
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ATSAM4L8/L4/L2 Supply Pin GPIO 64-pin GPIO Controller Function Multiplexing for WLCSP package (Sheet 3 of 3) ATSAM4LS ATSAM4LC Table 3-3.
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ATSAM4L8/L4/L2 1 PA00 0 VDDIO 2 2 PA01 1 VDDIO 3 3 PA02 2 VDDIN 10 10 PA03 3 VDDIN 11 11 PA04 4 VDDANA ADCIFE AD0 USART0 CLK EIC EXTINT2 GLOC IN1 12 12 PA05 5 VDDANA ADCIFE AD1 USART0 RXD EIC EXTINT3 GLOC IN2 ADCIFE TRIGGER CATB SENSE1 15 15 PA06 6 VDDANA DACC VOUT USART0 RTS EIC EXTINT1 GLOC IN0 ACIFC ACAN0 CATB SENSE2 16 16 PA07 7 VDDANA ADCIFE AD2 USART0 TXD EIC EXTINT4 GLOC IN3 ACIFC ACAP0 CATB SENSE3 20 20 PA08 8 LCDA USART0 RTS TC0 A0
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ATSAM4L8/L4/L2 Pin 44 44 PA24 24 LCDC SPI NPCS0 TWIMS0 TWCK 46 46 PA25 25 VDDIO USBC DM USART2 RXD CATB SENSE19 47 47 PA26 26 VDDIO USBC DP USART2 TXD CATB SENSE20 25 PA27 27 LCDA SPI MISO IISC ISCK ABDACB DAC0 GLOC IN4 USART3 RTS CATB SENSE0 26 PA28 28 LCDA SPI MOSI IISC ISDI ABDACB DACN0 GLOC IN5 USART3 CTS CATB SENSE1 27 PA29 29 LCDA SPI SCK IISC IWS ABDACB DAC1 GLOC IN6 USART3 CLK CATB SENSE2 30 PA30 30 LCDA SPI NPCS0 IISC ISDO ABDACB DACN1 G
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ATSAM4L8/L4/L2 3.2.4 ITM Trace Connections If the ITM trace is enabled, the ITM will take control over the pin PA23, irrespectively of the I/O Controller configuration. The Serial Wire Trace signal is available on pin PA23 3.2.5 Oscillator Pinout The oscillators are not mapped to the normal GPIO functions and their muxings are controlled by registers in the System Control Interface (SCIF) or Backup System Control Interface (BSCIF). Refer to the Section 15.
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ATSAM4L8/L4/L2 3.3 Signals Description The following table gives details on signal names classified by peripheral. Table 3-8.
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ATSAM4L8/L4/L2 Table 3-8.
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ATSAM4L8/L4/L2 Table 3-8.
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ATSAM4L8/L4/L2 Table 3-8. Signal Descriptions List (Sheet 4 of 4) Signal Name Function PA31 - PA00 Parallel I/O Controller I/O Port A I/O PB15 - PB00 Parallel I/O Controller I/O Port B I/O PC31 - PC00 Parallel I/O Controller I/O Port C I/O Note: 1. See “Power and Startup Considerations” section. 3.4 I/O Line Considerations 3.4.
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ATSAM4L8/L4/L2 3.4.7 ADC Input Pins These pins are regular I/O pins powered from the VDDANA.
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ATSAM4L8/L4/L2 4. Cortex-M4 processor and core peripherals 4.1 Cortex-M4 The Cortex-M4 processor is a high performance 32-bit processor designed for the microcontroller market.
PAGE 37
ATSAM4L8/L4/L2 sor core and NVIC provides fast execution of interrupt service routines (ISRs), dramatically reducing the interrupt latency. This is achieved through the hardware stacking of registers, and the ability to suspend load-multiple and store-multiple operations. Interrupt handlers do not require wrapping in assembler code, removing any code overhead from the ISRs. A tail-chain optimization also significantly reduces the overhead when switching from one ISR to another.
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ATSAM4L8/L4/L2 4.4 Cortex-M4 processor features and benefits summary • • • • • • • • • • • 4.
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ATSAM4L8/L4/L2 4.6 Cortex-M4 implementations options This table provides the specific configuration options implemented in the SAM4L series Option Inclusion of MPU yes Inclusion of FPU No Number of interrupts 80 Number of priority bits 4 Inclusion of the WIC No Embedded Trace Macrocell No Sleep mode instruction Only WFI supported Endianness Little Endian Bit-banding No SysTick timer Yes Register reset values No Table 4-1. 4.
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ATSAM4L8/L4/L2 Table 4-2. Line Interrupt Request Signal Map (Sheet 2 of 3) Module Signal 12 Peripheral DMA Controller PDCA 11 13 Peripheral DMA Controller PDCA 12 14 Peripheral DMA Controller PDCA 13 15 Peripheral DMA Controller PDCA 14 16 Peripheral DMA Controller PDCA 15 17 CRC Calculation Unit CRCCU 18 USB 2.
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ATSAM4L8/L4/L2 Table 4-2.
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ATSAM4L8/L4/L2 4.8 Peripheral Debug The PDBG register controls the behavior of asynchronous peripherals when the device is in debug mode.When the corresponding bit is set, that peripheral will be in a frozenstate in debug mode. 4.8.
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ATSAM4L8/L4/L2 5. Memories 5.1 Product Mapping Figure 5-1.
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ATSAM4L8/L4/L2 5.
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ATSAM4L8/L4/L2 Start Address Size Memory ATSAM4Lx8 Table 5-2.
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ATSAM4L8/L4/L2 6. Power and Startup Considerations Power Domain Overview VDDCORE VDDOUT GND ATSAM4LS Power Domain Diagram BUCK/LDOn (PA02) Figure 6-1. VDDIN 6.
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ATSAM4L8/L4/L2 VDDCORE VDDOUT GND VDDIN ATSAM4LC Power Domain Diagram BUCK/LDOn (PA02) Figure 6-2.
PAGE 48
ATSAM4L8/L4/L2 6.2 Power Supplies The ATSAM4L8/L4/L2 has several types of power supply pins: • VDDIO: Powers I/O lines, the general purpose oscillator (OSC), the 80MHz integrated RC oscillator (RC80M) . Voltage is 1.68V to 3.6V. • VLCDIN: (ATSAM4LC only) Powers the LCD voltage pump. Voltage is 1.68V to 3.6V. • VDDIN: Powers the internal voltage regulator. Voltage is 1.68V to 3.6V.
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ATSAM4L8/L4/L2 6.2.2 Typical Powering Schematics The ATSAM4L8/L4/L2 supports the Single supply mode from 1.68V to 3.6V. Depending on the input voltage range and on the final application frequency, it is recommended to use the following table in order to choose the most efficient power strategy Figure 6-3. Efficient power strategy: 1.68V 1.80V Switching Mode N/A (BUCK/LDOn (PA02) =1) Linear Mode (BUCK/LDOn (PA02) =0) 2.00V VDDIN Voltage 2.
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ATSAM4L8/L4/L2 The internal regulator is connected to the VDDIN pin and its output VDDOUT feeds VDDCORE in linear mode or through an inductor in switching mode. Figure 6-4 shows the power schematics to be used. All I/O lines will be powered by the same power (VVDDIN=VVDDIO=VVDDANA). Figure 6-4. Single Supply Mode VLCDIN Main Supply (1.68V-3.6V) VDDIO VDDANA BUCK/LDOn (PA02) LCD VPUMP RC80M, OSC, ADC, DAC, AC0/1, RC32K, OSC32K, BOD18, BOD33 VDDIN VDDOUT VDDCORE 6.2.3 6.2.3.
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ATSAM4L8/L4/L2 GND BIASL BIASH VLCD CAPL CAPH 55 54 53 52 51 CAPH 56 VLCDIN SEG0 58 VLCD 57 SEG1 59 CAPL SEG2 60 BIASH SEG3 GND BIASL SEG4 61 VLCDIN SEG5 62 63 SEG0 SEG2 SEG6 SEG7 64 SEG3 SEG1 SEG8 65 SEG4 SEG9 66 67 SEG5 SEG12 70 SEG10 SEG6 SEG13 71 SEG11 SEG14 72 68 SEG7 SEG15 73 69 SEG16 74 SEG8 SEG17 75 LCD clusters in the device SEG27 82 SEG10 SEG28 83 SEG29 84 SEG30 85 SEG31 VDDIO VDDIO 88 SEG32 89 45 SEG22 50 31 COM1 44 SEG23
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ATSAM4L8/L4/L2 connected to an external voltage source (1.8-3.6V). LCDB cluster is not available in 64 and 48 pin packages Table 6-1. LCD powering when using the internal voltage pump Package 100-pin packages Segments in use VDDIO VDDIO LCDB LCDC [1,24] 1.8-3.6V 1.8-3.6V [1, 32] nc 1.8-3.6V [1, 40] nc nc [1,15] - 1.8-3.6V [1, 23] - nc [1,9] - 1.8-3.
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ATSAM4L8/L4/L2 6.2.4 Power-up Sequence 6.2.4.1 Maximum Rise Rate To avoid risk of latch-up, the rise rate of the power supplies must not exceed the values described in Table 9-3 on page 100. 6.2.4.2 Minimum Rise Rate The integrated Power-on Reset (POR33) circuitry monitoring the VDDIN powering supply requires a minimum rise rate for the VDDIN power supply. See Table 9-3 on page 100 for the minimum rise rate value.
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ATSAM4L8/L4/L2 Figure 6-6. Supply Monitor Schematic DUAL OUTPUT TRIMMABLE VOLTAGE REGULATOR VDDCORE VDDANA POR33 BOD33 POR18 BOD18 VDDANA GNDANA 6.4.1 Power-on-Reset on VDDANA POR33 monitors VDDANA. It is always activated and monitors voltage at startup but also during all the Power Save Mode. If VDDANA goes below the threshold voltage, the entire chip is reset. 6.4.2 Brownout Detector on VDDANA BOD33 monitors VDDANA. Refer to Section 15.
PAGE 55
ATSAM4L8/L4/L2 7. Low Power Techniques The ATSAM4L8/L4/L2 supports multiple power configurations to allow the user to optimize its power consumption in different use cases. The Backup Power Manager (BPM) implements different solutions to reduce the power consumption: • The Power Save modes intended to reduce the logic activity and to adapt the power configuration. See ”Power Save Modes” on page 55. • The Power Scaling intended to scale the power configuration (voltage scaling of the regulator).
PAGE 56
ATSAM4L8/L4/L2 At power-up or after a reset, the ATSAM4L8/L4/L2 is in the RUN0 mode. Only the necessary clocks are enabled allowing software execution. The Power Manager (PM) can be used to adjust the clock frequencies and to enable and disable the peripheral clocks. When the CPU is entering a Power Save Mode, the CPU stops executing code.
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ATSAM4L8/L4/L2 mechanism can be useful for applications that only require the processor to run when an interrupt occurs. Before entering the SLEEP mode, the user must configure: • the SLEEP mode configuration field (BPM.PMCON.SLEEP), Refer to Table 7-1. • the SCR.SLEEPDEEP bit to 0. (See the Power Management section in the ARM Cortex-M4 Processor chapter). • the BPM.PMCON.RET bit to 0. • the BPM.PMCON.BKUP bit to 0. 7.1.1.2 7.1.
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ATSAM4L8/L4/L2 7.1.3 BACKUP Mode The BACKUP mode allows achieving the lowest power consumption possible in a system which is performing periodic wake-ups to perform tasks but not requiring fast startup time. The Core domain is powered-off. The internal SRAM and register contents of the Core domain are lost. The Backup domain is kept powered-on. The 32kHz clock (RC32K or OSC32K) is kept running if enabled to feed modules that require clocking. In BACKUP mode, the configuration of the I/O lines is preserved.
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ATSAM4L8/L4/L2 7.1.4 Wakeup Time 7.1.4.1 Wakeup Time From SLEEP Mode The latency depends on the clock sources wake up time. If the clock sources are not stopped, there is no latency to wake the clocks up. 7.1.4.2 Wakeup Time From WAIT or RETENTION Mode The wake up latency consists of: • the switching time from the low power configuration to the RUN mode power configuration. By default, the switching time is completed when all the voltage regulation system is ready.
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ATSAM4L8/L4/L2 7.1.5 Power Save Mode Summary Table The following table shows a summary of the main Power Save modes: Table 7-2. Mode Power Save mode Configuration Summary Mode Entry Wake up sources Core domain CPU clock OFF WFI SLEEP SCR.SLEEPDEEP bit = 0 Any interrupt BPM.PMCON.BKUP bit = 0 Other clocks OFF depending on the BPM.PMCON.SLEEP field see ”SLEEP mode” on page 56 Backup domain Clocks OFF depending on the BPM.PMCON.SLEEP field see ”SLEEP mode” on page 56 WFI SCR.
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ATSAM4L8/L4/L2 • Set the clock frequency to be supported in both power configurations. • Set the high speed read mode of the FLASH to be supported in both power scaling configurations – Only relevant when entering or exiting BPM.PMCON.PS=2 • Configure the BPM.PMCON.PS field to the new power configuration. • Set the BPM.PMCON.PSCREQ bit to one. • Disable all the interrupts except the PM WCAUSE interrupt and enable only the PSOK asynchronous event in the AWEN register of PM. • Execute the WFI instruction.
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ATSAM4L8/L4/L2 8. Debug and Test 8.1 Features • • • • • • • • • • • • 8.2 IEEE1149.
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ATSAM4L8/L4/L2 8.3 Block diagram Figure 8-1.
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ATSAM4L8/L4/L2 8.5 8.5.1 Product dependencies I/O Lines Refer to Section 1.1.5.1 ”I/O Lines” on page 5. 8.5.2 Power management Refer to Section 1.1.5.2 ”Power Management” on page 5. 8.5.3 Clocks Refer to Section 1.1.5.3 ”Clocks” on page 5. 8.6 Core debug Figure 8-2 shows the Debug Architecture used in the SAM4L.
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ATSAM4L8/L4/L2 The FPB unit contains: • Two literal comparators for matching against literal loads from Code space, and remapping to a corresponding area in System space. • Six instruction comparators for matching against instruction fetches from Code space and remapping to a corresponding area in System space. • Alternatively, comparators can also be configured to generate a Breakpoint instruction to the processor core on a match. 8.6.
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ATSAM4L8/L4/L2 – Fix the ATB ID to 1 • Write 0x1 into the Trace Enable Register: – Enable the Stimulus port 0 • Write 0x1 into the Trace Privilege Register: – Stimulus port 0 only accessed in privileged mode (Clearing a bit in this register will result in the corresponding stimulus port being accessible in user mode.) • Write into the Stimulus port 0 register: TPIU (Trace Port Interface Unit) The TPIU acts as a bridge between the on-chip trace data and the Instruction Trace Macrocell (ITM).
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ATSAM4L8/L4/L2 8.7 Enhanced Debug Port (EDP) Rev.: 1.0.0.0 8.7.1 Features • • • • • 8.7.2 IEEE1149.1 compliant JTAG debug port Serial Wire Debug Port Boundary-Scan chain on all digital pins for board-level testing Debugger Hot-Plugging SMAP core reset request source Overview The enhanced debug port embeds a standard ARM debug port plus some specific hardware intended for testability and activation of the debug port features.
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ATSAM4L8/L4/L2 8.7.3 Block Diagram Figure 8-3. Enhanced Debug Port Block Diagram ENHANCED DEBUG PORT SWJ-DP TMS swdio TDI traceswo SW-DP TDO swclk TCK DAP Bus tms tdi JTAG-DP tdo tck tms test_tap_sel tdi BSCAN-TAP boundary_scan JTAG-FILTER EDP Core reset request tdo tck tck reset_n RESET_N 8.7.4 I/O Lines Description Table 8-1.
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ATSAM4L8/L4/L2 8.7.5 8.7.5.1 Product Dependencies I/O Lines The TCK pin is dedicated to the EDP. The other debug port pins default after reset to their GPIO functionality and are automatically reassigned to the JTAG functionalities on detection of a debugger. In serial wire mode, TDI and TDO can be used as GPIO functions. Note that in serial wire mode TDO can be used as a single pin trace output. 8.7.5.2 Power Management When a debugger is present, the connection is kept alive allowing debug operations.
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ATSAM4L8/L4/L2 The Debug Port pins assignation is then forced to the EDP function even if they were already assigned to another module. This allows to connect a debugger at any time without reseting the device. The connection is non-intrusive meaning that the chip will continue its execution without being disturbed. The CPU can of course be halted later on by issuing Cortex-M4 OCD features. 8.7.
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ATSAM4L8/L4/L2 8.7.10 SW-DP and JTAG-DP Selection Mechanism After reset, the SWJ-DP is in JTAG mode but it can be switched to the Serial Wire mode. Debug port selection mechanism is done by sending specific SWDIOTMS sequence. The JTAG-DP is selected by default after reset. • Switch from JTAG-DP to SW-DP.
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ATSAM4L8/L4/L2 8.7.12 JTAG Instructions Summary The implemented JTAG instructions are shown in the table below. Table 8-2. IR instruction value Implemented JTAG instructions list Instruction Description availability when protected b0000 EXTEST Select boundary-scan chain as data register for testing circuitry external to the device. yes b0001 SAMPLE_PRELOAD Take a snapshot of external pin values without affecting system operation.
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ATSAM4L8/L4/L2 8.7.13 Security Restrictions The SAM4L provide a security restrictions mechanism to lock access to the device. The device in the protected state when the Flash Security Bit is set. Refer to section Flash Controller for more details. When the device is in the protected state the AHB-AP is locked. Full access to the AHB-AP is reenabled when the protected state is released by issuing a Chip Erase command.
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ATSAM4L8/L4/L2 Table 8-4. 8.7.14 8.7.14.1 Instruction Description (Continued) Instruction Description DR Size Shows the number of bits in the data register chain when this instruction is active. Example: 32 bits DR input value Shows which bit pattern to shift into the data register in the Shift-DR state when this instruction is active. DR output value Shows the bit pattern shifted out of the data register in the Shift-DR state when this instruction is active.
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ATSAM4L8/L4/L2 1. Select the IR Scan path. 2. In Capture-IR: The IR output value is latched into the shift register. 3. In Shift-IR: The instruction register is shifted by the TCK input. 4. Return to Run-Test/Idle. 5. Select the DR Scan path. 6. In Capture-DR: The Data on the external pins are sampled into the boundary-scan chain. 7. In Shift-DR: The boundary-scan chain is shifted by the TCK input. 8. Return to Run-Test/Idle. Table 8-6. 8.7.14.
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ATSAM4L8/L4/L2 8.7.14.4 CLAMP This instruction selects the Bypass register as Data Register. The device output pins are driven from the boundary-scan chain. Starting in Run-Test/Idle, the CLAMP instruction is accessed the following way: 1. Select the IR Scan path. 2. In Capture-IR: The IR output value is latched into the shift register. 3. In Shift-IR: The instruction register is shifted by the TCK input. 4. In Update-IR: The data from the boundary-scan chain is applied to the output pins. 5.
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ATSAM4L8/L4/L2 8.8 AHB-AP Access Port The AHB-AP is a Memory Access Port (MEM-AP) as defined in the ARM Debug Interface v5 Architecture Specification. The AHB-AP provides access to all memory and registers in the system, including processor registers through the System Control Space (SCS). System access is independent of the processor status. Either SW-DP or SWJ-DP is used to access the AHB-AP. The AHB-AP is a master into the Bus Matrix.
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ATSAM4L8/L4/L2 8.9 System Manager Access Port (SMAP) Rev.: 1.0.0.0 8.9.1 Features • • • • • 8.9.2 Chip Erase command and status Cortex-M4 core reset source 32-bit Cyclic Redundancy check of any memory accessible through the bus matrix Unlimited Flash User page read access Chip identification register Overview The SMAP provides memory-related services and also Cortex-M4 core reset control to a debugger through the Debug Port. This makes possible to halt the CPU and program the device after reset. 8.9.
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ATSAM4L8/L4/L2 8.9.6 Security Considerations In protected state this module may access sensible information located in the device memories. To avoid any risk of sensible data extraction from the module registers, all operations are non interruptible except by a disable command triggered by writing a one to CR.DIS. Issuing this command clears all the interface and internal registers.
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ATSAM4L8/L4/L2 8.9.9 Unlimited Flash User Page Read Access The SMAP can access the User page even if the protected state is set. Prior to operate such an access, the user should check that the module is not busy by checking that SR.STATE is equal to zerp. Once the offset of the word to access inside the page is written in ADDR.ADDR, the read operation can be initiated by writing a one in CR.FSPR. The SR.STATE field will indicate the FSPR state. Addresses written to ADDR.ADDR must be world aligned.
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ATSAM4L8/L4/L2 8.9.11 SMAP User Interface Table 8-9.
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ATSAM4L8/L4/L2 8.9.11.1 Name: Control Register CR Access Type: Write-Only Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - CE FSPR CRC DIS EN Writing a zero to a bit in this register has no effect.
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ATSAM4L8/L4/L2 8.9.11.
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ATSAM4L8/L4/L2 0: No bus error has been detected sincle last clear of this bit • HCR: Hold Core reset 1: The Cortex-M4 core is held under reset 0: The Cortex-M4 core is not held under reset • DONE: Operation done 1: At least one operation has terminated since last clear of this field 0: No operation has terminated since last clear of this field 84 42023GS–SAM–03/2014
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ATSAM4L8/L4/L2 8.9.11.3 Name: Status Clear Register SCR Access Type: Write-Only Offset: 0x08 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - LCK FAIL BERR HCR DONE Writing a zero to a bit in this register has no effect.
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ATSAM4L8/L4/L2 8.9.11.
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ATSAM4L8/L4/L2 8.9.11.
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ATSAM4L8/L4/L2 8.9.11.
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ATSAM4L8/L4/L2 8.9.11.7 Name: Module Version VERSION Access Type: Read-Only Offset: 0x28 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 1 0 VARIANT 11 10 VERSION 3 2 VERSION • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
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ATSAM4L8/L4/L2 8.9.11.8 Name: Chip Identification Register CIDR Access Type: Read-Only Offset: 0xF0 Reset Value: - 31 30 29 EXT 23 28 27 NVPTYP 22 21 20 19 18 24 17 16 9 8 1 0 SRAMSIZ 14 13 12 11 10 NVPSIZ2 7 25 ARCH ARCH 15 26 6 NVPSIZ 5 EPROC 4 3 2 VERSION Note: Refer to section CHIPID for more information on this register.
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ATSAM4L8/L4/L2 8.9.11.9 Name: Chip Identification Extension Register EXID Access Type: Read-Only Offset: 0xF4 Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 EXID 23 22 21 20 EXID 15 14 13 12 EXID 7 6 5 4 EXID Note: Refer to section CHIPID for more information on this register.
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ATSAM4L8/L4/L2 8.9.11.
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ATSAM4L8/L4/L2 8.10 Available Features in Protected State Table 8-10.
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ATSAM4L8/L4/L2 8.11 8.11.1 Functional Description Debug Environment Figure 8-8 shows a complete debug environment example. The SWJ-DP interface is used for standard debugging functions, such as downloading code and single-stepping through the program and viewing core and peripheral registers. Figure 8-8. Application Debug Environment Example Host Debugger PC SWJ-DP Emulator/Probe SWJ-DP Connector SAM4 SAM4-based Application Board 8.11.
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ATSAM4L8/L4/L2 Figure 8-9. Application Test Environment Example Test Adaptor Tester JTAG Probe JTAG Connector SAM4 Chip n Chip 2 Chip 1 SAM4-based Application Board In Test 8.11.3 How to initialize test and debug features To enable the JTAG pins a falling edge event must be detected on the TCK pin at any time after the RESET_N pin is released. Certain operations requires that the system is prevented from running code after reset is released.
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ATSAM4L8/L4/L2 Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is latched onto the parallel output from the shift register path in the Update-IR state. The Exit-IR, Pause-IR, and Exit2-IR states are only used for navigating the state machine. Figure 8-10. Scanning in JTAG instruction TCK TAP State TLR RTI SelDR SelIR CapIR ShIR Ex1IR UpdIR RTI TMS TDI TDO 8.11.5.
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ATSAM4L8/L4/L2 instruction for the first time. SAMPLE/PRELOAD can also be used for taking a snapshot of the external pins during normal operation of the part. When using the JTAG interface for Boundary-Scan, the JTAG TCK clock is independent of the internal chip clock, which is not required to run. NOTE: For pins connected to 5V lines care should be taken to not drive the pins to a logic one using boundary scan, as this will create a current flowing from the 3,3V driver to the 5V pullup on the line.
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ATSAM4L8/L4/L2 8.11.8 Chip erase typical procedure The chip erase operation is triggered by writing a one in the CE bit in the Control Register (CR.CE). This clears first all volatile memories in the system and second the whole flash array. Note that the User page is not erased in this process. To ensure that the chip erase operation is completed, check the DONE bit in the Status Register (SR.DONE).
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ATSAM4L8/L4/L2 9. Electrical Characteristics 9.1 Absolute Maximum Ratings* Table 9-1. Absolute Maximum Ratings Operating temperature..................................... -40°C to +85°C *NOTICE: Storage temperature...................................... -60°C to +150°C Voltage on input pins with respect to ground ..........................-0.3V to VVDD (1)+0.3V Total DC output current on all I/O pins VDDIO .........................................................................
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ATSAM4L8/L4/L2 Table 9-3. Supply Rise Rates and Order (1) VDDIO, VDDIN and VDDANA must be connected together and as a consequence, rise synchronously Rise Rate Symbol Parameter Min Max Unit VVDDIO DC supply peripheral I/Os 0.0001 2.5 V/µs VVDDIN DC supply peripheral I/Os and internal regulator 0.0001 2.5 V/µs VVDDANA Analog supply voltage 0.0001 2.5 V/µs 1. Comment These values are based on characterization. These values are not covered by test limits in production.
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ATSAM4L8/L4/L2 9.4 Maximum Clock Frequencies Table 9-4.
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ATSAM4L8/L4/L2 Table 9-5. Maximum Clock Frequencies in Power Scaling Mode 1 and RUN Mode Symbol Parameter Description Max fCPU CPU clock frequency 12 fPBA PBA clock frequency 12 fPBB PBB clock frequency 12 fPBC PBC clock frequency 12 fPBD PBD clock frequency 12 fGCLK0 GCLK0 clock frequency DFLLIF main reference, GCLK0 pin 16.6 fGCLK1 GCLK1 clock frequency DFLLIF dithering and SSGreference, GCLK1 pin 16.6 fGCLK2 GCLK2 clock frequency AST, GCLK2 pin 6.
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ATSAM4L8/L4/L2 9.5 Power Consumption 9.5.1 Power Scaling 0 and 2 The values in Table 9-6 are measured values of power consumption under the following conditions, except where noted: • Operating conditions for power scaling mode 0 and 2 – VVDDIN = 3.3V – Power Scaling mode 0 is used for CPU frequencies under 36MHz – Power Scaling mode 2 is used for CPU frequencies above 36MHz • Wake up time from low power modes is measured from the edge of the wakeup signal to the first instruction fetched in flash.
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ATSAM4L8/L4/L2 Table 9-6. ATSAM4L4/2 Current consumption and Wakeup time for power scaling mode 0 and 2 Max (1) 3817 4033 3934 4174 2341 2477 2437 2585 1758 1862 1847 1971 Linear mode 51 60 OSC32K and AST running Fast wake-up enable 5.9 8.7 4.7 7.6 3.1 5.1 AST and OSC32K stopped 2.2 4.2 OSC32K running AST running at 1kHz 1.5 3.1 AST and OSC32K stopped 0.9 1.
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ATSAM4L8/L4/L2 Table 9-7. ATSAM4L8 Current consumption and Wakeup time for power scaling mode 0 and 2 Max (1) 3817 4033 4050 4507 2341 2477 2525 2832 1758 1862 1925 1971 Linear mode 51 60 OSC32K and AST running Fast wake-up enable 6.
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ATSAM4L8/L4/L2 – All other peripheral clocks stopped • I/Os are inactive with internal pull-up • CPU is running on flash with 1 wait state • Low power cache enabled • BOD18 and BOD33 disabled Table 9-8.
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ATSAM4L8/L4/L2 Table 9-9. Mode ATSAM4L8 Current consumption and Wakeup time for power scaling mode 1 Typical Wakeup Time Typ Max (1) 222 240 233 276 233 276 230 270 100 112 100 119 104 128 107 138 527 627 579 739 369 445 404 564 305 381 334 442 Linear mode 46 55 OSC32K and AST running Fast wake-up enable 5.
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ATSAM4L8/L4/L2 Table 9-10. RCSYS (MCSEL = 0) Typical Power Consumption running CoreMark on CPU clock sources (1) Power scaling mode 1 0.115 978 0.5 354 12 114 12 228 30 219 0.
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ATSAM4L8/L4/L2 Figure 9-1. Note: Typical Power Consumption running Coremark (from above table) For variable frequency oscillators, linear interpolation between high and low settings Figure 9-2.
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ATSAM4L8/L4/L2 9.5.3 Peripheral Power Consumption in Power Scaling mode 0 and 2 The values in Table 9-11 are measured values of power consumption under the following conditions: • Operating conditions, internal core supply (Figure 9-2) – VVDDIN = 3.
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ATSAM4L8/L4/L2 Table 9-11. Peripheral Typ Consumption Active IISC 1.0 SPI 1.9 TC 6.3 TWIM 1.5 TWIS 1.2 USART ADCIFE ACIFC Unit 8.5 (2) DACC 9.5.4 Typical Current Consumption by Peripheral in Power Scaling Mode 0 and 2 (1) 3.1 1.3 (2) 3.1 GLOC 0.4 ABDACB 0.7 TRNG 0.9 PARC 0.7 CATB 3.0 LCDCA 4.4 PDCA 1.0 CRCCU 0.3 USBC 1.5 PEVC 5.6 CHIPID 0.1 SCIF 6.4 FREQM 0.5 GPIO 7.1 BPM 0.9 BSCIF 4.6 AST 1.5 WDT 1.4 EIC 0.6 PICOUART 0.3 µA/MHz 1.
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ATSAM4L8/L4/L2 • Operating conditions, internal core supply (Figure 9-2) – VVDDIN = 3.3V – VVDDCORE = 1.
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ATSAM4L8/L4/L2 Table 9-12. Peripheral Typical Current Consumption by Peripheral in Power Scaling Mode 1 (1) Typ Consumption Active IISC 0.5 SPI 1.1 TC 3.1 TWIM 0.8 TWIS 0.7 USART ADCIFE 4.4 (2) DACC ACIFC Unit 1.6 0.6 (2) 1.6 GLOC 0.1 ABDACB 0.3 TRNG 0.3 PARC 0.3 CATB 1.5 LCDCA 2.2 PDCA 0.4 CRCCU 0.3 USBC 0.9 PEVC 2.8 CHIPID 0.1 SCIF 3.1 FREQM 0.2 GPIO 3.4 BPM 0.4 BSCIF 2.3 AST 0.8 WDT 0.8 EIC 0.3 PICOUART 0.2 µA/MHz 1.
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ATSAM4L8/L4/L2 9.6 I/O Pin Characteristics 9.6.1 Normal I/O Pin Table 9-13. Normal I/O Pin Characteristics (1) Symbol Parameter RPULLUP Pull-up resistance (2) Conditions Min (2) Typ Max 40 kΩ 40 kΩ RPULLDOWN Pull-down resistance VIL Input low-level voltage -0.3 0.2 * VVDD VIH Input high-level voltage 0.8 * VVDD VVDD + 0.3 VOL Output low-level voltage VOH Output high-level voltage VVDD - 0.
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ATSAM4L8/L4/L2 3. These values are based on characterization. These values are not covered by test limits in production 9.6.2 High-drive I/O Pin : PA02, PC04, PC05, PC06 Table 9-14. High-drive I/O Pin Characteristics (1) Symbol Parameter Conditions Min (2) Typ Max RPULLUP Pull-up resistance RPULLDOWN Pull-down resistance(2) VIL Input low-level voltage -0.3 0.2 * VVDD VIH Input high-level voltage 0.8 * VVDD VVDD + 0.
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ATSAM4L8/L4/L2 9.6.3 USB I/O Pin : PA25, PA26 Table 9-15. USB I/O Pin Characteristics in GPIO configuration (1) Symbol Parameter Conditions Min (2) Typ Max RPULLUP Pull-up resistance RPULLDOWN Pull-down resistance(2) VIL Input low-level voltage -0.3 0.2 * VVDD VIH Input high-level voltage 0.8 * VVDD VVDD + 0.
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ATSAM4L8/L4/L2 Table 9-16. Symbol TWI Pin Characteristics in TWI configuration (1) Parameter Conditions Current Source(3) ICS Min Typ DRIVEH=0 0.5 DRIVEH=1 1 DRIVEH=2 1.5 DRIVEH=3 3 Max mA fMAX Max frequency(2) HsMode with Current source; DRIVEx=3, SLEW=0 Cbus = 400pF, VVDD = 1.68V tRISE Rise time(2) HsMode Mode, DRIVEx=3, SLEW=0 Cbus = 400pF, Rp = 440Ohm, VVDD = 1.68V 28 38 Standard Mode, DRIVEx=3, SLEW=0 Cbus = 400pF, Rp = 440Ohm, VVDD = 1.
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ATSAM4L8/L4/L2 Table 9-17. Symbol TWI Pin Characteristics in GPIO configuration (1) Parameter Conditions OSRR0=0 OSRR0=1 Rise time(2) tRISE OSRR0=0 OSRR0=1 OSRR0=0 OSRR0=1 Fall time(2) tFALL OSRR0=0 OSRR0=1 Min Typ Max Units 18 ODCR0=0 1.68V
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ATSAM4L8/L4/L2 9.6.5 High Drive TWI Pin : PB00, PB01 Table 9-19. High Drive TWI Pin Characteristics in TWI configuration (1) Symbol Parameter Conditions (2) Min Typ Max RPULLUP Pull-up resistance RPULLDOWN Pull-down resistance(2) VIL Input low-level voltage -0.3 0.3 * VVDD VIH Input high-level voltage 0.7 * VVDD VVDD + 0.3 VOL Output low-level voltage VOH Output high-level voltage IOL ICS Output low-level current (3) Current Source(2) PB00, PB01 40 kΩ 40 kΩ VVDD - 0.
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ATSAM4L8/L4/L2 Table 9-20. Symbol High Drive TWI Pin Characteristics in GPIO configuration (1) Parameter Conditions Min Typ Max Units Pull-up resistance (2) 40 kΩ RPULLDOWN Pull-up resistance (2) 40 kΩ VIL Input low-level voltage -0.3 0.2 * VVDD VIH Input high-level voltage 0.8 * VVDD VVDD + 0.3 VOL Output low-level voltage VOH Output high-level voltage RPULLUP VVDD - 0.
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ATSAM4L8/L4/L2 9.7 Oscillator Characteristics 9.7.1 Oscillator 0 (OSC0) Characteristics 9.7.1.1 Digital Clock Characteristics The following table describes the characteristics for the oscillator when a digital clock is applied on XIN. Table 9-22. Digital Clock Characteristics Symbol Parameter fCPXIN XIN clock frequency (1) tCPXIN XIN clock duty cycle(1) tSTARTUP Startup time 1. Conditions Min Typ 40 Max Units 50 MHz 60 % N/A cycles These values are based on simulation.
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ATSAM4L8/L4/L2 Table 9-23. Symbol CL Crystal Oscillator Characteristics Parameter Conditions Crystal load capacitance Typ 6 Crystal shunt capacitance Parasitic capacitor load CXOUT Parasitic capacitor load(2) tSTARTUP Startup time(1) pF 4.91 TQFP100 package 3.22 Current consumption(1) SCIF.OSCCTRL.GAIN = 2 30 000 (3) Active mode, f = 0.6MHz, SCIF.OSCCTRL.GAIN = 0 30 Active mode, f = 4MHz, SCIF.OSCCTRL.GAIN = 1 130 Active mode, f = 8MHz, SCIF.OSCCTRL.
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ATSAM4L8/L4/L2 9.7.2 32kHz Crystal Oscillator (OSC32K) Characteristics Figure 9-3 and the equation above also applies to the 32kHz oscillator connection. The user must choose a crystal oscillator where the crystal load capacitance CL is within the range given in the table. The exact value of CL can then be found in the crystal datasheet. Table 9-24. Symbol fCPXIN32 Digital Clock Characteristics Parameter Conditions XIN32 clock frequency XIN32 clock duty cycle(1) tSTARTUP 1.
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ATSAM4L8/L4/L2 9.7.3 Phase Locked Loop (PLL) Characteristics Table 9-26. Symbol Phase Locked Loop Characteristics Parameter Conditions (1) fOUT Output frequency fIN Input frequency(1) IPLL Current consumption(1) tSTARTUP Startup time, from enabling the PLL until the PLL is locked(1) 1. PLL is not availabe in PS1 Typ Max 48 240 4 16 Unit MHz fout=80MHz 200 fout=240MHz 500 µA Wide Bandwidth mode disabled 8 Wide Bandwidth mode enabled 30 µs These values are based on simulation.
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ATSAM4L8/L4/L2 Table 9-27. Symbol Digital Frequency Locked Loop Characteristics Parameter tSTARTUP Startup time Conditions (1) Typ Within 90% of final values fREF = 32kHz, FINE lock, SSG disabled Lock time(1) tLOCK Min (2) Max Unit 100 µs 600 fREF = 32kHz, ACCURATE lock, dithering clock = RCSYS/2, SSG disabled(2) 1100 1. These values are based on simulation. These values are not covered by test limits in production or characterization. 2.
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ATSAM4L8/L4/L2 9.7.7 1MHz RC Oscillator (RC1M) Characteristics Table 9-30. Symbol RC1M Oscillator Characteristics Parameter Conditions (1) fOUT Output frequency IRC1M Current consumption (2) Duty Duty cycle(1) Min Typ Max Unit 0.91 1 1.12 MHz 35 48.6 49.9 µA 54.4 1. These values are based on characterization. These values are not covered by test limits in production. 2. These values are based on simulation.
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ATSAM4L8/L4/L2 9.7.9 80MHz RC Oscillator (RC80M) Characteristics Table 9-32. Internal 80MHz RC Oscillator Characteristics Symbol Parameter Conditions Min Typ Max Unit fOUT Output frequency (1) After calibration Note that RC80M is not available in PS1 60 80 100 MHz IRC80M Current consumption (2) tSTARTUP Startup time 330 (1) (2) Duty Duty cycle µA 0.57 1.72 3.2 µs 45 50 55 % 1. These values are based on characterization.
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ATSAM4L8/L4/L2 1. These values are based on simulation. These values are not covered by test limits in production or characterization. Table 9-35. Flash Endurance and Data Retention (1) Symbol Parameter Conditions Min NFARRAY Array endurance (write/page) fCLK_AHB > 10MHz 100k NFFUSE General Purpose fuses endurance (write/bit) fCLK_AHB > 10MHz 10k tRET Data retention 1. Typ Max Unit cycles 15 years These values are based on simulation.
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ATSAM4L8/L4/L2 9.9 Analog Characteristics 9.9.1 Voltage Regulator Characteristics Table 9-36. VREG Electrical Characteristics in Linear and Switching Modes Symbol Parameter DC output current (1) Power scaling mode 0 & 2 IOUT VVDDCORE Typ Max Low power mode (WAIT) 2000 3600 5600 Ultra Low power mode (RETENTION) 100 180 300 Low power mode (WAIT) 4000 7000 10000 Ultra Low power mode (RETENTION) 200 350 600 Units DC output voltage All modes 1.
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ATSAM4L8/L4/L2 Table 9-39. Symbol IOUT VREG Electrical Characteristics in Switching mode Parameter DC output current Conditions (1) Typ VVDDCORE > 1.65V (1) Max Units 55 mA Output DC load regulation Transient load regulation IOUT = 0 to 50mA, VVDDIN = 3V -136 -101 -82 mV Output DC regulation(1) IOUT = 50 mA, VVDDIN = 2V to 3.6V -20 38 99 mV VVDDIN = 2V, IOUT = 0 mA 97 186 546 VVDDIN > 2.2V, IOUT = 0 mA 97 111 147 82.7 88.
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ATSAM4L8/L4/L2 9.9.2 Power-on Reset 33 Characteristics Table 9-41. POR33 Characteristics (1) Symbol Parameter VPOT+ Voltage threshold on VVDDIN rising 1.25 1.55 VPOT- Voltage threshold on VVDDIN falling 0.95 1.30 1. Conditions Min Typ Max Units V These values are based on characterization. These values are not covered by test limits in production. POR33 Operating Principle VVDDIN Figure 9-4. VPOT+ VPOT- Reset Time 9.9.3 Brown Out Detectors Characteristics Table 9-42.
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ATSAM4L8/L4/L2 1. These values are based on simulation. These values are not covered by test limits in production or characterization. The values in Table 9-43 describe the values of the BOD33.LEVEL in the flash User Page fuses. Table 9-43. BOD33.LEVEL Values BOD33.LEVEL Value Table 9-44. Min Typ Max 16 2.08 20 2.18 24 2.33 28 2.48 32 2.62 36 2.77 40 2.92 44 3.06 48 3.
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ATSAM4L8/L4/L2 9.9.4 Analog- to Digital Converter Characteristics Table 9-45. Symbol Operating conditions Parameter Conditions Min Temperature range Resolution Typ -40 (1) Max Sampling clock (3) fADC ADC clock frequency(3) TSAMPLEHOLD Sampling time(3) 12 Max Units +85 °C 12 (2) Differential modes, Gain=1X 5 300 Unipolar modes, Gain=1X 5 250 Differential modes 0.03 1.8 Unipolar modes 0.03 1.5 Differential modes 16.5 277 Unipolar modes 16.
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ATSAM4L8/L4/L2 Table 9-46. Symbol VDDANA DC Characteristics Parameter Supply voltage Conditions Max Units 1.6 3.6 V Differential mode 1.0 VDDANA -0.6 Unipolar and Window modes 1.0 1.0 Using divide by two function (differential) 2.0 VDDANA -0,1 VDDANA +0.1 V 24 Cycles No gain compensation Reference buffer 5 µs Gain compensation Reference buffer 60 Cycles 0.5 kΩ 4.
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ATSAM4L8/L4/L2 Table 9-47. Differential mode, gain=1 Offset error drift vs temperature(1) Conversion range (2) Vin-Vip -Vref mV/°K Vref V see Figure 9-5 ICMR(1) PSRR 0.04 (1) DC supply current (2) fvdd=1Hz, ext ADVREFP=3.0V VVDD=3.6V 100 fvdd=2MHz, ext ADVREFP=3.0V VVDD=3.6 50 VDDANA=3.6V, ADVREFP=3.0V 1.2 VDDANA=1.6V, ADVREFP=1.0V 0.6 dB mA 1. These values are based on simulation only. These values are not covered by test limits in production or characterization 2.
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ATSAM4L8/L4/L2 Table 9-48. Unipolar mode, gain=1 PSRR(1) DC supply current (1) fVdd=100kHz, VDDIO=3.6V 62 fVdd=1MHz, VDDIO=3.6V 49 VDDANA=3.6V 1 2 VDDANA=1.6V, ADVREFP=1.0V 1 1.3 dB mA 1. These values are based on simulation. These values are not covered by test limits in production or characterization. 2. These values are based on characterization and not tested in production, and valid for an input voltage between 10% to 90% of reference voltage. 9.9.4.
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ATSAM4L8/L4/L2 9.9.5 Digital to Analog Converter Characteristics Table 9-49. Symbol Operating conditions Parameter Analog Supply Voltage Digital Supply Voltage Resolution (1) (1) Conditions Min Typ Max Units on VDDANA 2.4 3 3.6 V on VDDCORE 1.62 1.8 1.
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ATSAM4L8/L4/L2 Table 9-50. Symbol Analog Comparator Characteristics Parameter Hysteresis(1) Propagation delay(1) tSTARTUP IAC 1. Startup time (1) Channel current consumption (3) Conditions Min VACREFN =0.1V to VDDIO-0.1V, hysteresis = 1(2) Fast mode Typ Max Units 10 55 mV VACREFN =0.1V to VDDIO-0.1V, hysteresis = 1(2) Low power mode 10 68 mV VACREFN =0.1V to VDDIO-0.1V, hysteresis = 2(2) Fast mode 26 83 mV VACREFN =0.1V to VDDIO-0.
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ATSAM4L8/L4/L2 9.9.7 Liquid Crystal Display Controler characteristics Table 9-51. Liquid Crystal Display Controler characteristics Symbol Parameter SEG Segment Terminal Pins 40 COM Common Terminal Pins 4 fFrame LCD Frame Frequency CFlying Flying Capacitor VLCD Conditions FCLKLCD Min Typ 31.25 512 100 Units Hz nF 3 LCD Regulated Voltages (1) CFG.FCST=0 BIAS2 CFlying = 100nF 100nF on VLCD, BIAS2 and BIAS1 pins 2*VLCD/3 V VLCD/3 BIAS1 1. Max These values are based on simulation.
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ATSAM4L8/L4/L2 9.10 Timing Characteristics 9.10.1 RESET_N Timing Table 9-53. RESET_N Waveform Parameters (1) Symbol Parameter tRESET RESET_N minimum pulse length 1. Conditions Min 10 Max Units ns These values are based on simulation. These values are not covered by test limits in production. 9.10.2 9.10.2.1 USART in SPI Mode Timing Master mode Figure 9-7. USART in SPI Master Mode with (CPOL= CPHA= 0) or (CPOL= CPHA= 1) SPCK MISO USPI0 USPI1 MOSI USPI2 Figure 9-8.
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ATSAM4L8/L4/L2 Table 9-54. Symbol USART0 in SPI Mode Timing, Master Mode(1) Parameter USPI0 MISO setup time before SPCK rises USPI1 MISO hold time after SPCK rises USPI2 SPCK rising to MOSI delay USPI3 MISO setup time before SPCK falls USPI4 MISO hold time after SPCK falls USPI5 SPCK falling to MOSI delay Table 9-55.
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ATSAM4L8/L4/L2 Maximum SPI Frequency, Master Output The maximum SPI master output frequency is given by the following formula: 1 f CLKSPI × 2 f SPCKMAX = MIN (f PINMAX,------------, -----------------------------) SPIn 9 Where SPIn is the MOSI delay, USPI2 or USPI5 depending on CPOL and NCPHA. f PINMAX is the maximum frequency of the SPI pins. refer to the I/O Pin Characteristics section for the maximum frequency of the pins. f CLKSPI is the maximum frequency of the CLK_SPI.
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ATSAM4L8/L4/L2 Figure 9-10. USART in SPI Slave Mode with (CPOL= CPHA= 0) or (CPOL= CPHA= 1) SPCK MISO USPI9 MOSI USPI10 USPI11 Figure 9-11. USART in SPI Slave Mode, NPCS Timing USPI12 USPI13 USPI14 USPI15 SPCK, CPOL=0 SPCK, CPOL=1 NSS Table 9-58. USART0 in SPI mode Timing, Slave Mode(1) Symbol Parameter USPI6 SPCK falling to MISO delay Conditions Min Max 740.67 tSAMPLE(2) USPI7 MOSI setup time before SPCK rises 56.73 + tCLK_USART USPI8 MOSI hold time after SPCK rises 45.
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ATSAM4L8/L4/L2 Table 9-59. USART1 in SPI mode Timing, Slave Mode(1) Symbol Parameter USPI6 SPCK falling to MISO delay USPI7 MOSI setup time before SPCK rises USPI8 MOSI hold time after SPCK rises USPI9 SPCK rising to MISO delay USPI10 MOSI setup time before SPCK falls USPI11 MOSI hold time after SPCK falls USPI12 NSS setup time before SPCK rises USPI13 NSS hold time after SPCK falls USPI14 NSS setup time before SPCK falls USPI15 NSS hold time after SPCK rises Table 9-60.
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ATSAM4L8/L4/L2 Table 9-61. USART3 in SPI mode Timing, Slave Mode(1) Symbol Parameter Conditions USPI6 SPCK falling to MISO delay Min Max 593.9 tSAMPLE(2) + USPI7 MOSI setup time before SPCK rises 45.93 + tCLK_USART USPI8 MOSI hold time after SPCK rises 47.03 -( tSAMPLE(2) + tCLK_USART ) USPI9 SPCK rising to MISO delay VVDDIO from 3.0V to 3.6V, maximum external capacitor = 40pF 593.38 tSAMPLE(2) 45.
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ATSAM4L8/L4/L2 9.10.3 SPI Timing 9.10.3.1 Master mode Figure 9-12. SPI Master Mode with (CPOL= NCPHA= 0) or (CPOL= NCPHA= 1) SPCK MISO SPI0 SPI1 MOSI SPI2 Figure 9-13. SPI Master Mode with (CPOL= 0 and NCPHA= 1) or (CPOL= 1 and NCPHA= 0) SPCK MISO SPI3 SPI4 MOSI SPI5 Table 9-62.
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ATSAM4L8/L4/L2 The maximum SPI master output frequency is given by the following formula: 1 f SPCKMAX = MIN (f PINMAX,------------) SPIn Where SPIn is the MOSI delay, SPI2 or SPI5 depending on CPOL and NCPHA. f PINMAX is the maximum frequency of the SPI pins. refer to the I/O Pin Characteristics section for the maximum frequency of the pins.
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ATSAM4L8/L4/L2 Figure 9-16. SPI Slave Mode, NPCS Timing SPI12 SPI13 SPI14 SPI15 SPCK, CPOL=0 SPCK, CPOL=1 NPCS Table 9-63.
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ATSAM4L8/L4/L2 Where SPIn is the MISO delay, SPI6 or SPI9 depending on CPOL and NCPHA. t SETUP is the SPI master setup time. refer to the SPI master datasheet for t SETUP . f PINMAX is the maximum frequency of the SPI pins. refer to the I/O Pin Characteristics section for the maximum frequency of the pins. 9.10.4 TWIM/TWIS Timing Figure 9-64 shows the TWI-bus timing requirements and the compliance of the device with them.
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ATSAM4L8/L4/L2 2. A device must internally provide a hold time of at least 300 ns for TWD with reference to the falling edge of TWCK. Notations: Cb = total capacitance of one bus line in pF tclkpb = period of TWI peripheral bus clock tprescaled = period of TWI internal prescaled clock (see chapters on TWIM and TWIS) The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW-TWI) of TWCK. 9.10.5 JTAG Timing Figure 9-17.
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ATSAM4L8/L4/L2 Table 9-65. JTAG Timings(1) Symbol Parameter JTAG0 TCK Low Half-period 21.8 JTAG1 TCK High Half-period 8.6 JTAG2 TCK Period 30.3 JTAG3 TDI, TMS Setup before TCK High JTAG4 TDI, TMS Hold after TCK High JTAG5 TDO Hold Time JTAG6 TCK Low to TDO Valid JTAG7 Boundary Scan Inputs Setup Time JTAG8 Boundary Scan Inputs Hold Time 6.9 JTAG9 Boundary Scan Outputs Hold Time 9.3 JTAG10 TCK to Boundary Scan Outputs Valid Note: Conditions VVDDIO from 3.0V to 3.
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ATSAM4L8/L4/L2 Table 9-66. SWD Timings(1) Symbol Parameter Thigh SWDCLK High period Tlow SWDCLK Low period Tos SWDIO output skew to falling edge SWDCLK Tis Input Setup time required between SWDIO Tih Input Hold time required between SWDIO and rising edge SWDCLK Note: Conditions VVDDIO from 3.0V to 3.6V, maximum external capacitor = 40pF Min Max 10 500 000 10 500 000 -5 5 4 - 1 - Units ns 1. These values are based on simulation.
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ATSAM4L8/L4/L2 10. Mechanical Characteristics 10.1 10.1.1 Thermal Considerations Thermal Data Table 10-1 summarizes the thermal resistance data depending on the package. Table 10-1. 10.1.2 Thermal Resistance Data Symbol Parameter Condition Package Typ θJA Junction-to-ambient thermal resistance Still Air TQFP100 48.1 θJC Junction-to-case thermal resistance TQFP100 13.3 θJA Junction-to-ambient thermal resistance VFBGA100 31.1 θJC Junction-to-case thermal resistance VFBGA100 6.
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ATSAM4L8/L4/L2 10.2 Package Drawings Figure 10-1. VFBGA-100 package drawing Table 10-2. Device and Package Maximum Weight 120 Table 10-3. mg Package Characteristics Moisture Sensitivity Level Table 10-4.
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ATSAM4L8/L4/L2 Figure 10-2. TQFP-100 Package Drawing Table 10-5. Device and Package Maximum Weight 500 Table 10-6. mg Package Characteristics Moisture Sensitivity Level Table 10-7.
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ATSAM4L8/L4/L2 Figure 10-3. WLCSP64 SAM4LC4/2 Package Drawing Table 10-8. Device and Package Maximum Weight 14.8 Table 10-9. mg Package Characteristics Moisture Sensitivity Level MSL3 Table 10-10.
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ATSAM4L8/L4/L2 Figure 10-4. WLCSP64 SAM4LS4/2 Package Drawing Table 10-11. Device and Package Maximum Weight 14.8 mg Table 10-12. Package Characteristics Moisture Sensitivity Level MSL3 Table 10-13.
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ATSAM4L8/L4/L2 Figure 10-5. WLCSP64 SAM4LC8 Package Drawing Table 10-14. Device and Package Maximum Weight 14.8 mg Table 10-15. Package Characteristics Moisture Sensitivity Level MSL3 Table 10-16.
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ATSAM4L8/L4/L2 Figure 10-6. WLCSP64 SAM4LS8 Package Drawing Table 10-17. Device and Package Maximum Weight 14.8 mg Table 10-18. Package Characteristics Moisture Sensitivity Level MSL3 Table 10-19.
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ATSAM4L8/L4/L2 Figure 10-7. TQFP-64 Package Drawing Table 10-20. Device and Package Maximum Weight 300 mg Table 10-21. Package Characteristics Moisture Sensitivity Level MSL3 Table 10-22.
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ATSAM4L8/L4/L2 Figure 10-8. QFN-64 Package Drawing Note: The exposed pad is not connected to anything internally, but should be soldered to ground to increase board level reliability. Table 10-23. Device and Package Maximum Weight 200 mg Table 10-24. Package Characteristics Moisture Sensitivity Level MSL3 Table 10-25.
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ATSAM4L8/L4/L2 Figure 10-9. TQFP-48 (ATSAM4LC4/2 and ATSAM4LS4/2 Only) Package Drawing Table 10-26. Device and Package Maximum Weight 140 mg Table 10-27. Package Characteristics Moisture Sensitivity Level MSL3 Table 10-28.
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ATSAM4L8/L4/L2 Figure 10-10. QFN-48 Package Drawing for ATSAM4LC4/2 and ATSAM4LS4/2 Note: The exposed pad is not connected to anything internally, but should be soldered to ground to increase board level reliability. Table 10-29. Device and Package Maximum Weight 140 mg Table 10-30. Package Characteristics Moisture Sensitivity Level MSL3 Table 10-31.
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ATSAM4L8/L4/L2 Figure 10-11. QFN-48 Package Drawing for ATSAM4LC8 and ATSAM4LS8 Note: The exposed pad is not connected to anything internally, but should be soldered to ground to increase board level reliability. Table 10-32. Device and Package Maximum Weight 140 mg Table 10-33. Package Characteristics Moisture Sensitivity Level MSL3 Table 10-34.
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ATSAM4L8/L4/L2 10.3 Soldering Profile Table 10-35 gives the recommended soldering profile from J-STD-20. Table 10-35.
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ATSAM4L8/L4/L2 11. Ordering Information Table 11-1.
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ATSAM4L8/L4/L2 Table 11-3.
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ATSAM4L8/L4/L2 Table 11-5.
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ATSAM4L8/L4/L2 12. Errata 12.1 12.1.1 ATSAM4L4 /2 Rev. B & ATSAM4L8 Rev. A General PS2 mode is not supported by Engineering Samples PS2 mode support is supported only by parts with calibration version higher than 0. Fix/Workaround The calibration version can be checked by reading a 32-bit word at address 0x0080020C. The calibration version bitfield is 4-bit wide and located from bit 4 to bit 7 in this word. Any value higher than 0 ensures that the part supports the PS2 mode 12.1.
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ATSAM4L8/L4/L2 Fix/Workaround Read the last received data, then perform a software reset by writing a one to the Software Reset bit in the Control Register (CR.SWRST). Disabling SPI has no effect on the SR.TDRE bit Disabling SPI has no effect on the SR.TDRE bit whereas the write data command is filtered when SPI is disabled. Writing to TDR when SPI is disabled will not clear SR.TDRE.
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ATSAM4L8/L4/L2 12.1.7 FLASHCALW Corrupted data in flash may happen after flash page write operations. After a flash page write operation, reading (data read or code fetch) in flash may fail. This may lead to an expecption or to others errors derived from this corrupted read access. Fix/Workaround Before any flash page write operation, each 64-bit doublewords write in the page buffer must preceded by a 64-bit doublewords write in the page buffer with 0xFFFFFFFF_FFFFFFFF content at any address in the page.
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ATSAM4L8/L4/L2 13. Datasheet Revision History Note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 13.1 13.2 13.3 13.4 Rev. A – 09/12 1. Initial revision. 1. Fixed ordering code 2. Changed BOD18CTRL and BOD33CTRL ACTION field from “Reserved” to ‘No action” 1. Fixed ball pitch for VFBGA100 package 2. Added VFBGA100 and WLCSP64 pinouts 3.
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ATSAM4L8/L4/L2 13.5 13.6 13.7 Rev. E – 07/13 1. Added ATSAM4L8 derivatives and WLCSP packages for ATSAM4L4/2 2. Added operating conditions details in Electrical Characteristics Chapter 3. Fixed “Supply Rise Rates and Order” 4. Added number of USART available in sub-series 5. Fixed IO line considerations for USB pins 6. Removed useless information about CPU local bus which is not implemented 7. Removed useless information about Modem support which is not implemented 8.
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ATSAM4L8/L4/L2 Table of Contents Summary.................................................................................................... 1 Features ..................................................................................................... 1 1 Description ............................................................................................... 3 2 Overview ................................................................................................... 5 3 4 5 6 7 2.
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ATSAM4L8/L4/L2 8 9 Debug and Test ...................................................................................... 62 8.1 Features ..........................................................................................................62 8.2 Overview ..........................................................................................................62 8.3 Block diagram ..................................................................................................63 8.
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13.4 Rev. D – 03/13 ...............................................................................................172 13.5 Rev. E – 07/13 ...............................................................................................173 13.6 Rev. F– 12/13 ................................................................................................173 13.7 Rev. G– 03/14 ...............................................................................................173 Table of Contents............