Datasheet

995
42023E–SAM–07/2013
ATSAM4L8/L4/L2
38.3 Block diagram
Figure 38-1. ADCIFE Block Diagram
38.4 I/O Lines Description
38.5 Product dependencies
38.5.1 I/O Lines
The pins used for interfacing the ADCIFE may be multiplexed with I/O Controller lines. The pro-
grammer must first program the I/O controller to assign the desired ADCIFE pins to their
AD0
AD1
AD2
ADn
Sequencer
ADCIFE
GCLK
GNDREF
GPIO Controller
Neg Analog mux
Trigger
Selection
Trigger/PEVC Sources
Timer
Interrupt Request
DMA request
Adcife_pevc_eoc
CLK_ADCIFE
User
Interface
Adcife_pevc_wm
12-bit
Cyclic
Pipeline
ADC
CORE
ADVREFP
Pos Analog mux
Peripheral Bus
Reference
Buffer
Clock
Generator
CLK_ADCIFE
Bandgap
External Ref.
Table 38-1. I/O Lines decription table
Name Description Type
AD0-AD14 Analog input channels Analog
External Ref. 2 External Voltage References Analog
A33VDD Analog power supply Power
A33GND Analog ground Power
ADTRG External trigger Digital