Datasheet

949
42023E–SAM–07/2013
ATSAM4L8/L4/L2
34.8 Module Configuration
The specific configuration for each CATB instance is listed in the following tables.The module
bus clocks listed here are connected to the system bus clocks. Refer to Section 10. ”Power Man-
ager (PM)” on page 108 for details.
Table 34-4. CATB Configuration
Feature CATB
Number of sensors/connected pins 32
Number of status bits in STATUSSEL 32
Number of fractional bits implemented in IDLE, LEVEL,
TIMING, and THRESH.
10
Number of available bits in the PINSEL register 5
Table 34-5. CATB Clocks
Clock Name Description
CLK_CATB Clock for the CATB bus interface
RC Oscillator Source clock for the CLK_ACQ
GCLK
Source clock for the CLK_ACQ. The
generic clock used for the CATB is
GCLK3
Table 34-6. Register Reset Values
Register Reset Value
VERSION 0x00000100
PARAMETER 0x000A2020