Datasheet

906
42023E–SAM–07/2013
ATSAM4L8/L4/L2
33.7.2 Mode Register
Name:
MR
Access: Read/Write
Offset: 0x04
Reset Value: 0x00000000
This register can only be written if the WPEN bit is cleared in Write Protect Mode Register.
• CLKDIV: Clock Divider for Internal Trigger
Trigger period is CLKDIV * APB clock period.
• STARTUP: Startup Time Selection
Starup time is (STARTUP + 1) * APB clock period.
• WORD: Word Transfer
• DACEN: DAC Enable
Writing a one to this bit enables the DAC.
Writing a zero to this bit disables the DAC.
• TRGSEL: Trigger Selection
• TRGEN: Trigger Enable
0: Internal trigger mode.
1: External trigger mode.
31 30 29 28 27 26 25 24
CLKDIV
23 22 21 20 19 18 17 16
CLKDIV
15 14 13 12 11 10 9 8
STARTUP
76543210
– – WORD DACEN TRGSEL TRGEN
WORD Selected Resolution
0 Half-Word transfer (16 bits)
1 Word Transfer (32 bits)
TRGSEL Selected TRGSEL
0 0 0 external trigger
0 0 1 peripheral event
010Reserved
011Reserved
100Reserved
101Reserved
110Reserved
111Reserved