Datasheet

873
42023E–SAM–07/2013
ATSAM4L8/L4/L2
31.9 Module Configuration
The specific configuration for each PEVC instance is listed in the following tables.
The module bus clocks listed here are connected to the system bus clocks. Refer to Section 10.
”Power Manager (PM)” on page 108 for details.
The module Register Reset Values are listed below.
The following table defines generators and input events connected to the Peripheral Event Sys-
tem. It also specifies whether Event Shaper and Input Glitch Filter are implemented for this
generator, and if SleepWalking is available.
Table 31-5. Module Clock Name
Module name Clock name
PEVC CLK_PEVC
Table 31-6. Register Reset Values
Register Reset Value
VERSION 0x00000200
PARAMETER 0x131F1204
BUSY 0x0002401F
Table 31-7. Generators
CHMXn.EVMX Generator - input event IGF EVS SleepWalking
0 PAD_EVT 0 - change on input pin Yes Yes Yes
1 PAD_EVT 1 - change on input pin Yes Yes Yes
2 PAD_EVT 2 - change on input pin Yes Yes Yes
3 PAD_EVT 3 - change on input pin Yes Yes Yes
4 GCLK 8 - rising edge Yes
5 GCLK 9 - rising edge Yes
6 AST - alarm event 0 Yes Yes
7Reserved
8 AST - periodic event 0 Yes Yes
9Reserved
10 AST - overflow event Yes Yes
11 ACIFC - AC0 VINP>VINN
12 ACIFC - AC1 VINP>VINN
13 ACIFC - AC2 VINP>VINN
14 ACIFC - AC3 VINP>VINN
15 ACIFC - AC0 VINP<VINN
16 ACIFC - AC1 VINP<VINN
17 ACIFC - AC2 VINP<VINN
18 ACIFC - AC3 VINP<VINN