Datasheet

861
42023E–SAM–07/2013
ATSAM4L8/L4/L2
31.8.9 Trigger Status Register
Name:
TRSR
Access Type: Read-only
Offset: 0x030
Reset Value: 0x00000000
• TRS: Trigger Interrupt Status
0: An interrupt event has not occurred
1: An interrupt event has occurred
This bit is cleared by writing a one to the corresponding bit in TRSCR.
31 30 29 28 27 26 25 24
TRS
23 22 21 20 19 18 17 16
TRS
15 14 13 12 11 10 9 8
TRS
76543210
TRS