Datasheet

852
42023E–SAM–07/2013
ATSAM4L8/L4/L2
31.8 User Interface
Notes: 1. The reset values for these registers are device specific. Refer to the Module Configuration section at the end of this chapter.
Table 31-4. PEVC Register Memory Map
Offset Register Register Name Access Reset
0x000 Channel Status Register CHSR Read-only 0x00000000
0x004 Channel Enable Register CHER Write-only -
0x008 Channel Disable Register CHDR Write-only -
0x010 Software Event SEV Write-only -
0x014 Channel / User Busy BUSY Read-only -
(1)
0x020 Trigger Interrupt Mask Enable Register TRIER Write-only -
0x024 Trigger Interrupt Mask Disable Register TRIDR Write-only -
0x028 Trigger Interrupt Mask Register TRIMR Read-only 0x00000000
0x030 Trigger Status Register TRSR Read-only 0x00000000
0x034 Trigger Status Clear Register TRSCR Write-only -
0x040 Overrun Interrupt Mask Enable Register OVIER Write-only -
0x044 Overrun Interrupt Mask Disable Register OVIDR Write-only -
0x048 Overrun Interrupt Mask Register OVIMR Read-only 0x00000000
0x050 Overrun Status Register OVSR Read-only 0x00000000
0x054 Overrun Status Clear Register OVSCR Write-only -
0x100 Channel Multiplexer 0 CHMX0 Read/Write 0x00000000
0x100
+ i*4
Channel Multiplexer i CHMXi Read/Write 0x00000000
0x17C Channel Multiplexer 31 CHMX31 Read/Write 0x00000000
0x200 Event Shaper 0 EVS0 Read/Write 0x00000000
0x200
+ j*4
Event Shaper j EVSj Read/Write 0x00000000
0x2FC Event Shaper 63 EVS63 Read/Write 0x00000000
0x300 Input Glitch Filter Divider Register IGFDR Read/Write 0x00000000
0x3F8 Parameter PARAMETER Read-only -
(1)
0x3FC Version VERSION Read-only -
(1)