Datasheet

743
42023E–SAM–07/2013
ATSAM4L8/L4/L2
28. Two-wire Slave Interface (TWIS)
Rev: 1.4.0.1
28.1 Features
• Compatible with I²C standard
– Transfer speeds up to 3.4 Mbit/s
– 7 and 10-bit and General Call addressing
• Compatible with SMBus standard
– Hardware Packet Error Checking (CRC) generation and verification with ACK response
– 25 ms clock low timeout delay
– 25 ms slave cumulative clock low extend time
• Compatible with PMBus
• DMA interface for reducing CPU load
• Arbitrary transfer lengths, including 0 data bytes
• Optional clock stretching if transmit or receive buffers not ready for data transfer
• 32-bit Peripheral Bus interface for configuration of the interface
28.2 Overview
The Atmel Two-wire Slave Interface (TWIS) interconnects components on a unique two-wire
bus, made up of one clock line and one data line with speeds of up to 3.4 Mbit/s, based on a
byte-oriented transfer format. It can be used with any Atmel Two-wire Interface bus, I²C, or
SMBus-compatible master. The TWIS is always a bus slave and can transfer sequential or sin-
gle bytes.
Below,
Table 28-1 lists the compatibility level of the Atmel Two-wire Slave Interface and a full I²C
compatible device.
Note: 1. START + b000000001 + Ack + Sr
Table 28-1. Atmel TWIS Compatibility with I²C Standard
I²C Standard Atmel TWIS
Standard-mode (100 kbit/s) Supported
Fast-mode (400 kbit/s) Supported
High-speed-mode (3.4 Mbit/s) Supported
7 or 10 bits Slave Addressing Supported
START BYTE
(1)
Not Supported
Repeated Start (Sr) Condition Supported
ACK and NAK Management Supported
Slope control and input filtering (Fast mode) Supported
Clock stretching Supported