Datasheet

742
42023E–SAM–07/2013
ATSAM4L8/L4/L2
27.10 Module Configuration
The specific configuration for each TWIM instance is listed in the following tables.The module
bus clocks listed here are connected to the system bus clocks. Refer to Section 10. ”Power Man-
ager (PM)” on page 108 for details.
Note : TWI2 and TWI3 are master only. TWI0 and TWI1 are master and slave
Table 27-7. Module Clock Name
Module Name Clock Name Description
TWIM0 CLK_TWIM0 Clock for the TWIM0 bus interface
TWIM1 CLK_TWIM1 Clock for the TWIM1 bus interface
TWIM2 CLK_TWIM2 Clock for the TWIM2 bus interface
TWIM3 CLK_TWIM3 Clock for the TWIM3 bus interface
Table 27-8. Register Reset Values
Register Reset Value
VERSION 0x00000120
PARAMETER 0x00000001