Datasheet

576
42023E–SAM–07/2013
ATSAM4L8/L4/L2
Figure 24-2. USART Block Diagram
Peripheral DMA
Controller
Channel Channel
Interrupt
Controller
Power
Manager
DIV
Receiver
Transmitter
User
Interface
I/O
Controller
RXD
RTS
TXD
CTS
CLK
BaudRate
Generator
USART
Interrupt
CLK_USART
CLK_USART/DIV
USART
Peripheral bus
Table 24-1. SPI Operating Mode
PIN USART SPI Slave SPI Master
RXD RXD MOSI MISO
TXD TXD MISO MOSI
RTS RTS – CS
CTS CTS CS –