Datasheet

572
42023E–SAM–07/2013
ATSAM4L8/L4/L2
23.8 Module Configuration
The specific configuration for each GPIO instance is listed in the following tables. The module
bus clocks listed here are connected to the system bus clocks. Refer to Section 10. ”Power Man-
ager (PM)” on page 108 for details.
The reset values for all GPIO registers are zero, with the following exceptions:
Table 23-3. GPIO Configuration
Feature
48 pin
package
64-pin
package
100-pin
package
Number of GPIO ports 1 2 3
Number of peripheral functions 8 8 8
Table 23-4. Implemented Pin Functions
Pin Function Implemented Notes
Pull-up On all pins Controlled by PUER or peripheral
Pull-down On all pins Controlled by PDER or peripheral
Slew Rate On all pins Controlled by OSRR or peripheral
Drive Strength On all pins Controlled by ODCR or peripheral
Schmitt Trigger Enable On all pins Controlled by STER or peripheral
Table 23-5. GPIO Clocks
Clock Name Description
CLK_GPIO Clock for the GPIO bus interface
Table 23-6. Register Reset Values
Port Register Reset Value
0 GPER 0xFFFFFFFF
0 PMR0 0x00000008
0 PMR1 0x00000000
0 PMR2 0x00000000
0 PUER 0x00000000
0 GFER 0x00000000
0 PARAMETER 0xFFFFFFFC
0 VERSION 0x00000215
1 GPER 0x0000FFFF
1 PMR0 0x00000000
1 PMR1 0x00000000