Datasheet

550
42023E–SAM–07/2013
ATSAM4L8/L4/L2
Note: 1. The reset values for these registers are device specific. Refer to the Module Configuration section at the end of this chapter.
0x110 Output Driving Capability Register 1 Read ODCR1 Read/Write -
(1)
Y N
0x114 Output Driving Capability Register 1 Set ODCR1S Write-only Y N
0x118 Output Driving Capability Register 1 Clear ODCR1C Write-only Y N
0x11C Output Driving Capability Register 1 Toggle ODCR1T Write-only Y N
0x130 Output Slew Rate Register 0 Read OSRR0 Read/Write Y N
0x134 Output Slew Rate Register 0 Set OSRR0S Write-only Y N
0x138 Output Slew Rate Register 0 Clear OSRR0C Write-only Y N
0x13C Output Slew Rate Register 0 Toggle OSRR0T Write-only Y N
0x160 Schmitt Trigger Enable Register Read STER Read/Write -
(1)
Y N
0x164 Schmitt Trigger Enable Register Set STERS Write-only Y N
0x168 Schmitt Trigger Enable Register Clear STERC Write-only Y N
0x16C Schmitt Trigger Enable Register Toggle STERT Write-only Y N
0x180 Event Enable Register Read EVER Read/Write -
(1)
N N
0x184 Event Enable Register Set EVERS Write-only N N
0x188 Event Enable Register Clear EVERC Write-only N N
0x18C Event Enable Register Toggle EVERT Write-only N N
0x1F8 Parameter Register Read PAR A ME TER Read-only -
(1)
N N
0x1FC Version Register Read VERSION Read-only -
(1)
N N
Table 23-2. GPIO Register Memory Map
Offset Register Function Register Name Access Reset
Config.
Protection
Access
Protection