Datasheet

5
42023E–SAM–07/2013
ATSAM4L8/L4/L2
2. Overview
2.1 Block Diagram
Figure 2-1. Block Diagram
BIASL,BIASH
CAPH,CAPL
ASYNCHRONOUS
TIMER
PERIPHERAL
DMA
CONTROLLER
HSB-PB
BRIDGE B
HSB-PB
BRIDGE A
S
MM
SM
EXTERNAL INTERRUPT
CONTROLLER
HIGH SPEED
BUS MATRIX
GENERALPURPOSE I/Os
GENERAL PURPOSE I/Os
PA
PB
PC
EXTINT[8..1]
NMI
PA
PB
PC
SPI
DMA
MISO, MOSI
NPCS[3..0]
USART0
USART1
USART2
USART3
DMA
RXD
TXD
CLK
RTS, CTS
WATCHDOG
TIMER
SCK
JTAG &
Serial Wire
TDO
TDI
TMS
CONFIGURATION REGISTERS BUS
S
ARM Cortex-M4 Processor
Fmax 48 MHz
In-Circuit
Emulator
NVIC
TWI MASTER 0
TWI MASTER 1
TWI MASTER 2
TWI MASTER 3
DMA
TWI SLAVE 0
TWI SLAVE 1
DMA
RESET
CONTROLLER
SLEEP
CONTROLLER
CLOCK
CONTROLLER
TCK
TWCK
TWD
TWCK
TWD
USBC
8 EndPoints
DMA
INTER-IC SOUND
CONTROLLER
AUDIO BITSTREAM
DAC
DMA
ABDAC[1..0]
ABDACN[1..0]
ISCK
IWS
ISDI
ISDO
IMCK
CLK
M
S
D
M
DP
SYSTEM CONTROL
INTERFACE
GCLK[3:0]
VDDCORE
VDDOUT
RCSYS
X
I
N
0
X
O
U
T
0
OSC0
DFLL
RC32K
PLL
GCLK_IN[1:0]
S
MEMORY PROTECTION UNIT
Instruction/
Data
System
System
TAP
HSB-PB
BRIDGE D
S
POWER MANAGER
RESETN
BACKUP
SYSTEM
CONTROL
INTERFACE
BACKUP
REGISTERS
CAPACITIVE TOUCH
MODULE
BACKUP
POWER MANAGER
LDO/
SWITCHING
REGULATOR
DMA
SENSE[69..0]
DIS
GLUE LOGIC
CONTROLLER
IN[7..0]
OUT[1..0]
TIMER/COUNTER 0
TIMER/COUNTER 1
A[2..0]
B[2..0]
CLK[2..0]
FREQUENCY METER
16-CHANNEL
12-bit ADC
INTERFACE
DMA
TRIGGER
AD[14..0]
ADVREFP
AC INTERFACE
ACREFN
ACAN[3..0]
ACAP[3..0]
HSB-PB
BRIDGE C
RCFAST
PARALLEL CAPTURE
CONTROLLER
S
BACKUP DOMAIN
PCCK
DMA
32-BIT CRC
CALCULATION UNIT
VDDIN
TRUE RANDOM
GENERATOR
10-bit DAC
INTERFACE
DMA
DACOUT
PICOUART
RXD
PCEN1,PCEN2
PCDATA[7..0]
LCD
CONTROLLER
SEG[39..0]
COM[3..0]
DMA
128-bit
AES
S
DMA
FLASH
CONTROLLER
LOW POWER CACHE
512/256/128 KB
FLASH
HRAM
CONTROLLER
64/32 KB
RAM
System
Management
Access Port
RC80M
X
I
N
3
2
X
O
U
T
3
2
OSC32
PERIPHERAL EVENT CONTROLLER
PAD_EVT[3..0]
GENERIC
CLOCK