Datasheet

472
42023E–SAM–07/2013
ATSAM4L8/L4/L2
19.6.13 Clock Control Register
Name:
CLOCK
Access Type: Read/Write
Offset: 0x40
Reset Value: 0x00000000
When writing to this register, follow the sequence in Section 19.5.1 on page 453.
• CSSEL: Clock Source Selection
This field defines the clock source CLK_AST_PRSC for the prescaler:
• CEN: Clock Enable
0: CLK_AST_PRSC is disabled.
1: CLK_AST_PRSC is enabled.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
- - - - - CSSEL
76543210
-------CEN
Table 19-2. Clock Source Selection
CSSEL Clock Source
0 System RC oscillator (RCSYS)
1 32kHz oscillator (OSC32 or RC32)
2 APB clock
3 Generic clock (GCLK)
4
1kHz clock from 32kHz oscillator or 32kHz
RC oscillator (CLK_1K)