Datasheet

260
42023E–SAM–07/2013
ATSAM4L8/L4/L2
.
15 CLK_1K 1kHz output clock from OSC32K
16 PLL0 Output clock from PLL0
17 HRP High Resolution Prescaler Output
18 FP Fractionnal Prescaler Output
19-20 GCLK_IN[0-1] GCLK_IN[0-1] pins, digital clock input
21 GCLK11
Generic Clock 11. Can not be use as
input to itself.
22-31 Reserved
Table 13-9. PLL Clock Sources
PLLOSC Clock/Oscillator Description
0 OSC0 Output clock from Oscillator0
1 GCLK9 Generic clock 9
2-3 Reserved
Table 13-10. Generic Clock number of DIV bits
Generic Clock Number of DIV bits
08
18
28
38
48
58
68
78
88
98
10 8
11 16
Table 13-8. Generic Clock Sources
OSCSEL Clock/Oscillator Description