Datasheet

165
42023E–SAM–07/2013
ATSAM4L8/L4/L2
Figure 12-2. BOD18/33 Block Diagram
The BOD18/33 is enabled by writing a one to the Enable bit in the BOD18/33 Control Register
(BOD18/33CTRL.EN). When enabled, the BOD18/33 output will be masked during half a Sys-
tem RC oscillator (RCSYS) clock cycle and an additional two CPU clock cycles, in order to avoid
false results. See
Section 42.9 ”Analog Characteristics” on page 1150 for parametric details.
12.6.3.1 Monitored Voltages
• VDDIO (BOD33)
• VDDCORE (BOD18)
12.6.3.2 Supported Modes
The BOD18/33 can operate in two different modes:
• Continuous mode
• Sampling mode
The Operation Mode bit in the Control Register (BOD18/33CTRL.MODE) is used to select the
mode of operation.
POWER
MANAGER (PM)
Interrupt
BOD33
VDDCORE
VDDANA
Reset
BOD33 Detected
Cont mode
Oneshot mode
BOD33 Hyst
BOD33 Level
BOD33 Reset
NVIC
BOD18
BOD18 Detected
Cont mode
Oneshot mode
BOD18 Hyst
BOD18 Level
BOD18 Reset
SCIF
BSCIF