Datasheet

140
42023E–SAM–07/2013
ATSAM4L8/L4/L2
11.3 Block Diagram
Figure 11-1. BPM Block Diagram
11.4 Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
11.4.1 Clocks
The clock for the BPM bus interface (CLK_BPM) is generated by the Power Manager. This clock
is enabled at reset, and can be disabled in the Power Manager.
BPM
VREGIF
PB Bus
PMCON
Configuration
BPM State Machine
Cortex-M4
BPM
interrupt
User Interface
GPIO
Controller
EIC
I/O Line
Management
Power Scaling
Power Save
Modes
WAKE UP
Management
Backup Reset
Backup
EIC Pins
CLK_BPM
NVIC
PM
Voltage
Regulator
EIC BOD33 BOD18 WDT AST
WFI
instruction
RCAUSE
BKUPMUX
Backup domain
BKUPWCAUSE
Standard
EIC Pins