Datasheet

121
42023E–SAM–07/2013
ATSAM4L8/L4/L2
10.7.5 Divided Clock Mask
Name: PBADIVMASK
Access Type: Read/Write
Offset: 0x040
Reset Value: 0x0000007F
• MASK: Clock Mask
If bit n is written to zero, the clock divided by 2
(n+1)
is stopped. If bit n is written to one, the clock divided by 2
(n+1)
is enabled
according to the current power mode. Table 10-6 shows what clocks are affected by the different MASK bits.
Note that this register is protected by a lock. To write to this register the UNLOCK register has to be written first. Refer to
Section 10.7.7 ”PM Unlock Register” on page 123 for details.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
- ------
15 14 13 12 11 10 9 8
--------
76543210
- MASK[6:0]
Table 10-6. Divided Clock Mask
Bit USART0 USART1 USART2 USART3 TC0 TC1
0----TIMER_CLOCK2TIMER_CLOCK2
1---- - -
2
CLK_USART/
DIV
CLK_USART/
DIV
CLK_USART/
DIV
CLK_USART/
DIV
TIMER_CLOCK3 TIMER_CLOCK3
3---- - -
4----TIMER_CLOCK4TIMER_CLOCK4
5---- - -
6----TIMER_CLOCK5TIMER_CLOCK5