Datasheet

1167
42023E–SAM–07/2013
ATSAM4L8/L4/L2
42.10.3 SPI Timing
42.10.3.1 Master mode
Figure 42-12. SPI Master Mode with (CPOL= NCPHA= 0) or (CPOL= NCPHA= 1)
Figure 42-13. SPI Master Mode with (CPOL= 0 and NCPHA= 1) or (CPOL= 1 and NCPHA= 0)
Note: 1. These values are based on simulation. These values are not covered by test limits in production.
Maximum SPI Frequency, Master Output
SPI0 SPI1
MISO
SPCK
MOSI
SPI2
SPI3 SPI4
MISO
SPCK
MOSI
SPI5
Table 42-62. SPI Timing, Master Mode
(1)
Symbol Parameter Conditions Min Max Units
SPI0 MISO setup time before SPCK rises
V
VDDIO
from
3.0V to 3.6V,
maximum
external
capacitor =
40pF
72.8 + (t
CLK_SPI
)/2
ns
SPI1 MISO hold time after SPCK rises 22.7
SPI2 SPCK rising to MOSI delay 47.4
SPI3 MISO setup time before SPCK falls 76.5 + (t
CLK_SPI
)/2
SPI4 MISO hold time after SPCK falls 20.6
SPI5 SPCK falling to MOSI delay 49.5