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Summary

Atmel's SAM4L series is a member of a family of Flash microcontrollers based

on the high performance 32-bit ARM Cortex-M4 RISC processor running at fre-

quencies up to 48MHz.

The SAM4L series embeds state-of-the-art picoPower technology for ultra-low

power consumption. Combined power control techniques are used to bring

active current consumption down to 90µA/MHz. The device allows a wide range

of options between functionality and power consumption, giving the user the

ability to reach the lowest possible power consumption with the feature set

required for the application. The WAIT and RETENTION modes provide full logic

and RAM retention, associated with fast wake-up capability (<1.5µs) and a very

low consumption of, respectively, 3 µA and 1.5 µA. In addition, WAIT mode sup-

ports SleepWalking features. In BACKUP mode, CPU, peripherals and RAM are

powered off and, while consuming less than 0.9µA with external interrupt wake-

up supported.

The SAM4L series offers a wide range of peripherals such as segment LCD con-

troller, embedded hardware capacitive touch (QTouch), USB device & embedded

host, 128-bit AES and audio interfaces in addition to high speed serial peripher-

als such as USART, SPI and I

C. Additionally the Peripheral Event System and

SleepWalking allows the peripherals to communicate directly with each other

and make intelligent decisions and decide to wake-up the system on a qualified

events on a peripheral level; such as I

C address match or and ADC threshold.

Features

• Core

– ARM

Cortex

-M4 running at up to 48MHz

– Memory Protection Unit (MPU)

–Thumb

-2 instruction set

• picoPower

Technology for Ultra-low Power Consumption

– Active mode downto 90µA/MHz with configurable voltage scaling

– High performance and efficiency: 28 coremark/mA

– Wait mode downto 3µA with fast wake-up time (<1.5µs) supporting SleepWalking

– Full RAM and Logic Retention mode downto 1.5µA with fast wake-up time (<1.5µs)

– Ultra low power Backup mode with/without RTC downto 1,5/0.9µA

• Memories

– From 128 to 512Kbytes embedded Flash, 64-bit wide access,

• 0 wait-state capability up to 24MHz

– up to 64Kbytes embedded SRAM

• System Functions

– Embedded voltage linear and switching regulator for single supply operation

– Two Power-on-Reset and Two Brown-out Detectors (BOD)

– Quartz or ceramic resonator oscillators: 0.6 to 30MHz main power with Failure

Detection and low power 32.768 kHz for RTC or device clock

– High precision 4/8/12MHz factory trimmed internal RC oscillator

– Slow Clock Internal RC oscillator as permanent low-power mode device clock

– High speed 80MHz internal RC oscillator

– Low power 32kHz internal RC oscillator

– PLL up to 240MHz for device clock and for USB

42023E–07/2013

ATSAM---e

ARM-based

Flash MCU

SAM4L Series

Summary of content (1204 pages)

PAGE 1
Summary Atmel's SAM4L series is a member of a family of Flash microcontrollers based on the high performance 32-bit ARM Cortex-M4 RISC processor running at frequencies up to 48MHz. The SAM4L series embeds state-of-the-art picoPower technology for ultra-low power consumption. Combined power control techniques are used to bring active current consumption down to 90µA/MHz.
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ATSAM4L8/L4/L2 • • • • – Digital Frequency Locked Loop (DFLL) with wide input range – Up to 16 peripheral DMA (PDCA) channels Peripherals – USB 2.0 Device and Embedded Host: 12 Mbps, up to 8 bidirectional Endpoints and Multi-packet Ping-pong Mode.
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ATSAM4L8/L4/L2 1. Description Atmel's SAM4L series is a member of a family of Flash microcontrollers based on the high performance 32-bit ARM Cortex-M4 RISC processor running at frequencies up to 48MHz. The processor implements a Memory Protection Unit (MPU) and a fast and flexible interrupt controller for supporting modern and real-time operating systems. The ATSAM4L8/L4/L2 embeds state-of-the-art picoPower technology for ultra-low power consumption.
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ATSAM4L8/L4/L2 The Power Manager (PM) improves design flexibility and security. The Power Manager supports SleepWalking functionality, by which a module can be selectively activated based on peripheral events, even in sleep modes where the module clock is stopped. Power monitoring is supported by on-chip Power-on Reset (POR18, POR33), Brown-out Detectors (BOD18, BOD33).
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ATSAM4L8/L4/L2 2. Overview 2.1 Block Diagram Figure 2-1.
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ATSAM4L8/L4/L2 2.2 Configuration Summary Table 2-1. Sub Series Summary Feature ATSAM4LC ATSAM4LS SEGMENT LCD Yes No AESA Yes No Device + Host Device Only USB Table 2-2.
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ATSAM4L8/L4/L2 Table 2-2. Configuration Summary Feature Oscillators ADC ATSAM4LxxC/ ATSAM4LxxB ATSAM4LxxA Digital Frequency Locked Loop 20-150MHz (DFLL) Phase Locked Loop 48-240MHz (PLL) Crystal Oscillator 0.
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ATSAM4L8/L4/L2 3. Package and Pinout 3.1 Package The device pins are multiplexed with peripheral functions as described in Section 3.2 ”Peripheral Multiplexing on I/O lines” on page 18. 3.1.1 ATSAM4LCx Pinout ATSAM4LC TQFP100 Pinout 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PB11 PB10 PB09 PB08 PC23 PC22 PC21 PC20 PA17 PA16 PA15 PA14 PA13 PC19 PC18 PC17 PC16 PC15 VLCDIN GND BIASL BIASH VLCD CAPL CAPH Figure 3-1.
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ATSAM4L8/L4/L2 Figure 3-2.
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ATSAM4L8/L4/L2 Figure 3-3.
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ATSAM4L8/L4/L2 ATSAM4LC TQFP64/QFN64 Pinout 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PB11 PB10 PB09 PB08 PA17 PA16 PA15 PA14 PA13 VLCDIN GND BIASL BIASH VLCD CAPL CAPH Figure 3-4.
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ATSAM4L8/L4/L2 ATSAM4LC TQFP48/QFN48 Pinout 36 35 34 33 32 31 30 29 28 27 26 25 PA17 PA16 PA15 PA14 PA13 VLCDIN GND BIASL BIASH VLCD CAPL CAPH Figure 3-5.
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ATSAM4L8/L4/L2 3.1.2 ATSAM4LSx Pinout ATSAM4LS TQFP100 Pinout 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PB11 PB10 PB09 PB08 PC23 PC22 PC21 PC20 PA17 PA16 PA15 PA14 PA13 PC19 PC18 PC17 PC16 PC15 PA31 PA30 VDDIO GND PA29 PA28 PA27 Figure 3-6.
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ATSAM4L8/L4/L2 Figure 3-7.
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ATSAM4L8/L4/L2 Figure 3-8.
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ATSAM4L8/L4/L2 ATSAM4LS TQFP64/QFN64 Pinout 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PB11 PB10 PB09 PB08 PA17 PA16 PA15 PA14 PA13 PA31 PA30 VDDIO GND PA29 PA28 PA27 Figure 3-9.
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ATSAM4L8/L4/L2 36 35 34 33 32 31 30 29 28 27 26 25 PA17 PA16 PA15 PA14 PA13 PA31 PA30 VDDIO GND PA29 PA28 PA27 Figure 3-10. ATSAM4LS TQFP48/QFN48 Pinout PA18 PA19 PA20 VDDIO PA21 PA22 PA23 PA24 VDDIO PA25 PA26 GND 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 PA12 PA11 PA10 PA09 PA08 VDDANA ADVREFP GNDANA PA07 PA06 XOUT32 XIN32 12 11 10 9 8 7 6 5 4 3 2 1 PA05 PA04 PA03 TCK VDDIN VDDOUT GND VDDCORE RESET_N PA02 PA01 PA00 See Section 3.
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ATSAM4L8/L4/L2 3.2 Peripheral Multiplexing on I/O lines 3.2.1 Multiplexed Signals Each GPIO line can be assigned to one of the peripheral functions. The following tables (Section 3-1 ”100-pin GPIO Controller Function Multiplexing” on page 18 to Section 3-4 ”48-pin GPIO Controller Function Multiplexing” on page 27) describes the peripheral signals multiplexed to the GPIO lines. Peripheral functions that are not relevant in some parts of the family are grey-shaded.
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ATSAM4L8/L4/L2 Supply Pin ATSAM4LC QFN GPIO 100-pin GPIO Controller Function Multiplexing (Sheet 2 of 4) ATSAM4LS Table 3-1.
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ATSAM4L8/L4/L2 Supply Pin ATSAM4LC QFN GPIO 100-pin GPIO Controller Function Multiplexing (Sheet 3 of 4) ATSAM4LS Table 3-1.
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ATSAM4L8/L4/L2 GPIO Pin ATSAM4LC QFN Supply 100-pin GPIO Controller Function Multiplexing (Sheet 4 of 4) ATSAM4LS Table 3-1.
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ATSAM4L8/L4/L2 Supply GPIO 64-pin GPIO Controller Function Multiplexing (Sheet 2 of 3) Pin ATSAM4LS ATSAM4LC Table 3-2.
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ATSAM4L8/L4/L2 Supply GPIO 64-pin GPIO Controller Function Multiplexing (Sheet 3 of 3) Pin ATSAM4LS ATSAM4LC Table 3-2.
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ATSAM4L8/L4/L2 64-pin GPIO Controller Function Multiplexing for WLCSP package (Sheet 1 of 3) Pin GPIO Supply ATSAM4LS ATSAM4LC Table 3-3.
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ATSAM4L8/L4/L2 Supply GPIO Pin 64-pin GPIO Controller Function Multiplexing for WLCSP package (Sheet 2 of 3) ATSAM4LS ATSAM4LC Table 3-3.
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ATSAM4L8/L4/L2 Supply GPIO Pin 64-pin GPIO Controller Function Multiplexing for WLCSP package (Sheet 3 of 3) ATSAM4LS ATSAM4LC Table 3-3.
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ATSAM4L8/L4/L2 1 PA00 0 VDDIO 2 2 PA01 1 VDDIO 3 3 PA02 2 VDDIN 10 10 PA03 3 VDDIN 11 11 PA04 4 VDDANA ADCIFE AD0 USART0 CLK EIC EXTINT2 GLOC IN1 12 12 PA05 5 VDDANA ADCIFE AD1 USART0 RXD EIC EXTINT3 GLOC IN2 ADCIFE TRIGGER CATB SENSE1 15 15 PA06 6 VDDANA DACC VOUT USART0 RTS EIC EXTINT1 GLOC IN0 ACIFC ACAN0 CATB SENSE2 16 16 PA07 7 VDDANA ADCIFE AD2 USART0 TXD EIC EXTINT4 GLOC IN3 ACIFC ACAP0 CATB SENSE3 20 20 PA08 8 LCDA USART0 RTS TC0 A0
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ATSAM4L8/L4/L2 Pin 44 44 PA24 24 LCDC SPI NPCS0 TWIMS0 TWCK 46 46 PA25 25 VDDIO USBC DM USART2 RXD CATB SENSE19 47 47 PA26 26 VDDIO USBC DP USART2 TXD CATB SENSE20 25 PA27 27 LCDA SPI MISO IISC ISCK ABDACB DAC0 GLOC IN4 USART3 RTS CATB SENSE0 26 PA28 28 LCDA SPI MOSI IISC ISDI ABDACB DACN0 GLOC IN5 USART3 CTS CATB SENSE1 27 PA29 29 LCDA SPI SCK IISC IWS ABDACB DAC1 GLOC IN6 USART3 CLK CATB SENSE2 30 PA30 30 LCDA SPI NPCS0 IISC ISDO ABDACB DACN1 G
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ATSAM4L8/L4/L2 3.2.4 ITM Trace Connections If the ITM trace is enabled, the ITM will take control over the pin PA23, irrespectively of the I/O Controller configuration. The Serial Wire Trace signal is available on pin PA23 3.2.5 Oscillator Pinout The oscillators are not mapped to the normal GPIO functions and their muxings are controlled by registers in the System Control Interface (SCIF) or Backup System Control Interface (BSCIF). Refer to the Section 13.
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ATSAM4L8/L4/L2 3.3 Signals Description The following table gives details on signal names classified by peripheral. Table 3-8.
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ATSAM4L8/L4/L2 Table 3-8.
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ATSAM4L8/L4/L2 Table 3-8.
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ATSAM4L8/L4/L2 Table 3-8. Signal Descriptions List (Sheet 4 of 4) Signal Name Function PA31 - PA00 Parallel I/O Controller I/O Port A I/O PB15 - PB00 Parallel I/O Controller I/O Port B I/O PC31 - PC00 Parallel I/O Controller I/O Port C I/O Note: 1. See “Power and Startup Considerations” section. 3.4 I/O Line Considerations 3.4.
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ATSAM4L8/L4/L2 3.4.7 ADC Input Pins These pins are regular I/O pins powered from the VDDANA.
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ATSAM4L8/L4/L2 4. Cortex-M4 processor and core peripherals 4.1 Cortex-M4 The Cortex-M4 processor is a high performance 32-bit processor designed for the microcontroller market.
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ATSAM4L8/L4/L2 sor core and NVIC provides fast execution of interrupt service routines (ISRs), dramatically reducing the interrupt latency. This is achieved through the hardware stacking of registers, and the ability to suspend load-multiple and store-multiple operations. Interrupt handlers do not require wrapping in assembler code, removing any code overhead from the ISRs. A tail-chain optimization also significantly reduces the overhead when switching from one ISR to another.
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ATSAM4L8/L4/L2 4.4 Cortex-M4 processor features and benefits summary • • • • • • • • • • • 4.
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ATSAM4L8/L4/L2 4.6 Cortex-M4 implementations options This table provides the specific configuration options implemented in the SAM4L series Option Inclusion of MPU yes Inclusion of FPU No Number of interrupts 80 Number of priority bits 4 Inclusion of the WIC No Embedded Trace Macrocell No Sleep mode instruction Only WFI supported Endianness Little Endian Bit-banding No SysTick timer Yes Register reset values No Table 4-1. 4.
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ATSAM4L8/L4/L2 Table 4-2. Line Interrupt Request Signal Map (Sheet 2 of 3) Module Signal 12 Peripheral DMA Controller PDCA 11 13 Peripheral DMA Controller PDCA 12 14 Peripheral DMA Controller PDCA 13 15 Peripheral DMA Controller PDCA 14 16 Peripheral DMA Controller PDCA 15 17 CRC Calculation Unit CRCCU 18 USB 2.
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ATSAM4L8/L4/L2 Table 4-2.
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ATSAM4L8/L4/L2 4.8 Peripheral Debug The PDBG register controls the behavior of asynchronous peripherals when the device is in debug mode.When the corresponding bit is set, that peripheral will be in a frozenstate in debug mode. 4.8.
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ATSAM4L8/L4/L2 5. Power and Startup Considerations Power Domain Overview VDDCORE VDDOUT GND ATSAM4LS Power Domain Diagram BUCK/LDOn (PA02) Figure 5-1. VDDIN 5.
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ATSAM4L8/L4/L2 VDDCORE VDDOUT GND VDDIN ATSAM4LC Power Domain Diagram BUCK/LDOn (PA02) Figure 5-2.
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ATSAM4L8/L4/L2 5.2 Power Supplies The ATSAM4L8/L4/L2 has several types of power supply pins: • VDDIO: Powers I/O lines, the general purpose oscillator (OSC), the 80MHz integrated RC oscillator (RC80M) . Voltage is 1.68V to 3.6V. • VLCDIN: (ATSAM4LC only) Powers the LCD voltage pump. Voltage is 1.68V to 3.6V. • VDDIN: Powers the internal voltage regulator. Voltage is 1.68V to 3.6V.
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ATSAM4L8/L4/L2 5.2.2 Typical Powering Schematics The ATSAM4L8/L4/L2 supports the Single supply mode from 1.68V to 3.6V. Depending on the input voltage range and on the final application frequency, it is recommended to use the following table in order to choose the most efficient power strategy Figure 5-3. Efficient power strategy: 1.68V 1.80V Switching Mode N/A (BUCK/LDOn (PA02) =1) 2.00V VDDIN Voltage 2.30V Possible but not efficient 3.
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ATSAM4L8/L4/L2 The internal regulator is connected to the VDDIN pin and its output VDDOUT feeds VDDCORE in linear mode or through an inductor in switching mode. Figure 5-4 shows the power schematics to be used. All I/O lines will be powered by the same power (VVDDIN=VVDDIO=VVDDANA). Figure 5-4. Single Supply Mode VLCDIN LCD VPUMP VDDIO RC80M, OSC, Main Supply (1.68V-3.
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ATSAM4L8/L4/L2 GND BIASL BIASH VLCD CAPL CAPH 55 54 53 52 51 VLCDIN 56 CAPH SEG0 58 VLCD 57 SEG1 59 CAPL SEG2 60 BIASH BIASL SEG3 GND SEG4 VLCDIN 61 SEG5 62 63 SEG0 SEG2 SEG6 SEG7 64 SEG3 SEG1 SEG8 65 SEG4 SEG9 66 67 SEG5 SEG12 70 SEG10 SEG6 SEG13 71 SEG11 SEG14 72 68 SEG7 SEG15 73 69 SEG16 74 SEG8 SEG17 75 LCD clusters in the device SEG27 82 SEG10 SEG28 83 SEG11 SEG29 84 SEG4 SEG3 SEG2 SEG1 SEG0 VLCDIN GND BIASL BIASH VLCD CAPL CAPH 33 49 34 S
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ATSAM4L8/L4/L2 connected to an external voltage source (1.8-3.6V). LCDB cluster is not available in 64 and 48 pin packages Table 5-1. LCD powering when using the internal voltage pump Package 100-pin packages Segments in use VDDIO VDDIO LCDB LCDC [1,24] 1.8-3.6V 1.8-3.6V [1, 32] nc 1.8-3.6V [1, 40] nc nc [1,15] - 1.8-3.6V [1, 23] - nc [1,9] - 1.8-3.
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ATSAM4L8/L4/L2 5.2.4 Power-up Sequence 5.2.4.1 Maximum Rise Rate To avoid risk of latch-up, the rise rate of the power supplies must not exceed the values described in Table 42-3 on page 1121. 5.2.4.2 Minimum Rise Rate The integrated Power-on Reset (POR33) circuitry monitoring the VDDIN powering supply requires a minimum rise rate for the VDDIN power supply. See Table 42-3 on page 1121 for the minimum rise rate value.
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ATSAM4L8/L4/L2 Figure 5-6. Supply Monitor Schematic DUAL OUTPUT TRIMMABLE VOLTAGE REGULATOR VDDCORE VDDANA POR33 BOD33 POR18 BOD18 VDDANA GNDANA 5.4.1 Power-on-Reset on VDDANA POR33 monitors VDDANA. It is always activated and monitors voltage at startup but also during all the Power Save Mode. If VDDANA goes below the threshold voltage, the entire chip is reset. 5.4.2 Brownout Detector on VDDANA BOD33 monitors VDDANA. Refer to Section 12.
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ATSAM4L8/L4/L2 6. Low Power Techniques The ATSAM4L8/L4/L2 supports multiple power configurations to allow the user to optimize its power consumption in different use cases. The Backup Power Manager (BPM) implements different solutions to reduce the power consumption: • The Power Save modes intended to reduce the logic activity and to adapt the power configuration. See ”Power Save Modes” on page 51. • The Power Scaling intended to scale the power configuration (voltage scaling of the regulator).
PAGE 52
ATSAM4L8/L4/L2 At power-up or after a reset, the ATSAM4L8/L4/L2 is in the RUN0 mode. Only the necessary clocks are enabled allowing software execution. The Power Manager (PM) can be used to adjust the clock frequencies and to enable and disable the peripheral clocks. When the CPU is entering a Power Save Mode, the CPU stops executing code.
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ATSAM4L8/L4/L2 mechanism can be useful for applications that only require the processor to run when an interrupt occurs. Before entering the SLEEP mode, the user must configure: • the SLEEP mode configuration field (BPM.PMCON.SLEEP), Refer to Table 6-1. • the SCR.SLEEPDEEP bit to 0. (See the Power Management section in the ARM Cortex-M4 Processor chapter). • the BPM.PMCON.RET bit to 0. • the BPM.PMCON.BKUP bit to 0. 6.1.1.2 6.1.
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ATSAM4L8/L4/L2 6.1.3 BACKUP Mode The BACKUP mode allows achieving the lowest power consumption possible in a system which is performing periodic wake-ups to perform tasks but not requiring fast startup time. The Core domain is powered-off. The internal SRAM and register contents of the Core domain are lost. The Backup domain is kept powered-on. The 32kHz clock (RC32K or OSC32K) is kept running if enabled to feed modules that require clocking. In BACKUP mode, the configuration of the I/O lines is preserved.
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ATSAM4L8/L4/L2 6.1.4 Wakeup Time 6.1.4.1 Wakeup Time From SLEEP Mode The latency depends on the clock sources wake up time. If the clock sources are not stopped, there is no latency to wake the clocks up. 6.1.4.2 Wakeup Time From WAIT or RETENTION Mode The wake up latency consists of: • the switching time from the low power configuration to the RUN mode power configuration. By default, the switching time is completed when all the voltage regulation system is ready.
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ATSAM4L8/L4/L2 6.1.5 Power Save Mode Summary Table The following table shows a summary of the main Power Save modes: Table 6-2. Mode Power Save mode Configuration Summary Mode Entry Wake up sources Core domain CPU clock OFF WFI SLEEP SCR.SLEEPDEEP bit = 0 Any interrupt BPM.PMCON.BKUP bit = 0 Other clocks OFF depending on the BPM.PMCON.SLEEP field see ”SLEEP mode” on page 52 Backup domain Clocks OFF depending on the BPM.PMCON.SLEEP field see ”SLEEP mode” on page 52 WFI SCR.
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ATSAM4L8/L4/L2 • Set the clock frequency to be supported in both power configurations. • Set the high speed read mode of the FLASH to be supported in both power scaling configurations – Only relevant when entering or exiting BPM.PMCON.PS=2 • Configure the BPM.PMCON.PS field to the new power configuration. • Set the BPM.PMCON.PSCREQ bit to one. • Disable all the interrupts except the PM WCAUSE interrupt and enable only the PSOK asynchronous event in the AWEN register of PM. • Execute the WFI instruction.
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ATSAM4L8/L4/L2 7. Memories 7.1 Product Mapping Figure 7-1.
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ATSAM4L8/L4/L2 7.
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ATSAM4L8/L4/L2 Start Address Size Memory ATSAM4Lx8 Table 7-2.
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ATSAM4L8/L4/L2 8. Debug and Test 8.1 Features • • • • • • • • • • • • 8.2 IEEE1149.
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ATSAM4L8/L4/L2 8.3 Block Diagram Figure 8-1. Debug and Test Block Diagram ENHANCED DEBUG PORT TMS TDI CORTEX-M4 TPIU PORT MUXING TDO Core AHB-AP SWJ-DP TCK Boundary scan Instr DAP Bus Data FPB BSCAN-TAP DWT NVIC ITM Hot_plugging JTAG-FILTER RESET_N Private peripheral Bus (PPB) M EDP Core reset request APB SMAP Core reset request HTOP AHB S SMAP Chip Erase M AHB AHB POR System Bus Matrix RESET CONTROLLER Cortex-M4 Core reset 8.4 I/O Lines Description Refer to Section 8.7.
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ATSAM4L8/L4/L2 8.5 8.5.1 Product Dependencies I/O Lines Refer to Section 8.7.5.1 ”I/O Lines” on page 68. 8.5.2 Power Management Refer to Section 8.7.5.2 ”Power Management” on page 68. 8.5.3 Clocks Refer to Section 8.7.5.3 ”Clocks” on page 68. 8.6 Core Debug Figure 8-2 shows the Debug Architecture used in the SAM4L.
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ATSAM4L8/L4/L2 The FPB unit contains: • Two literal comparators for matching against literal loads from Code space, and remapping to a corresponding area in System space. • Six instruction comparators for matching against instruction fetches from Code space and remapping to a corresponding area in System space. • Alternatively, comparators can also be configured to generate a Breakpoint instruction to the processor core on a match. 8.6.
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ATSAM4L8/L4/L2 – Fix the ATB ID to 1 • Write 0x1 into the Trace Enable Register: – Enable the Stimulus port 0 • Write 0x1 into the Trace Privilege Register: – Stimulus port 0 only accessed in privileged mode (Clearing a bit in this register will result in the corresponding stimulus port being accessible in user mode.) • Write into the Stimulus port 0 register: TPIU (Trace Port Interface Unit) The TPIU acts as a bridge between the on-chip trace data and the Instruction Trace Macrocell (ITM).
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ATSAM4L8/L4/L2 8.7 Enhanced Debug Port (EDP) Rev.: 1.0.0.0 8.7.1 Features • • • • • 8.7.2 IEEE1149.1 compliant JTAG debug port Serial Wire Debug Port Boundary-Scan chain on all digital pins for board-level testing Debugger Hot-Plugging SMAP core reset request source Overview The enhanced debug port embeds a standard ARM debug port plus some specific hardware intended for testability and activation of the debug port features.
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ATSAM4L8/L4/L2 8.7.3 Block Diagram Figure 8-3. Enhanced Debug Port Block Diagram ENHANCED DEBUG PORT SWJ-DP TMS swdio TDI traceswo SW-DP TDO swclk TCK DAP Bus tms tdi JTAG-DP tdo tck tms test_tap_sel tdi BSCAN-TAP boundary_scan JTAG-FILTER EDP Core reset request tdo tck tck reset_n RESET_N 8.7.4 I/O Lines Description Table 8-1.
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ATSAM4L8/L4/L2 8.7.5 8.7.5.1 Product Dependencies I/O Lines The TCK pin is dedicated to the EDP. The other debug port pins default after reset to their GPIO functionality and are automatically reassigned to the JTAG functionalities on detection of a debugger. In serial wire mode, TDI and TDO can be used as GPIO functions. Note that in serial wire mode TDO can be used as a single pin trace output. 8.7.5.2 Power Management When a debugger is present, the connection is kept alive allowing debug operations.
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ATSAM4L8/L4/L2 The Debug Port pins assignation is then forced to the EDP function even if they were already assigned to another module. This allows to connect a debugger at any time without reseting the device. The connection is non-intrusive meaning that the chip will continue its execution without being disturbed. The CPU can of course be halted later on by issuing Cortex-M4 OCD features. 8.7.
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ATSAM4L8/L4/L2 8.7.10 SW-DP and JTAG-DP Selection Mechanism After reset, the SWJ-DP is in JTAG mode but it can be switched to the Serial Wire mode. Debug port selection mechanism is done by sending specific SWDIOTMS sequence. The JTAG-DP is selected by default after reset. • Switch from JTAG-DP to SW-DP.
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ATSAM4L8/L4/L2 8.7.12 JTAG Instructions Summary The implemented JTAG instructions are shown in the table below. Table 8-2. IR instruction value Implemented JTAG instructions list Instruction Description availability when protected b0000 EXTEST Select boundary-scan chain as data register for testing circuitry external to the device. yes b0001 SAMPLE_PRELOAD Take a snapshot of external pin values without affecting system operation.
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ATSAM4L8/L4/L2 8.7.13 Security Restrictions The SAM4L provide a security restrictions mechanism to lock access to the device. The device in the protected state when the Flash Security Bit is set. Refer to section Flash Controller for more details. When the device is in the protected state the AHB-AP is locked. Full access to the AHB-AP is reenabled when the protected state is released by issuing a Chip Erase command.
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ATSAM4L8/L4/L2 Table 8-4. 8.7.14 8.7.14.1 Instruction Description (Continued) Instruction Description DR Size Shows the number of bits in the data register chain when this instruction is active. Example: 32 bits DR input value Shows which bit pattern to shift into the data register in the Shift-DR state when this instruction is active. DR output value Shows the bit pattern shifted out of the data register in the Shift-DR state when this instruction is active.
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ATSAM4L8/L4/L2 1. Select the IR Scan path. 2. In Capture-IR: The IR output value is latched into the shift register. 3. In Shift-IR: The instruction register is shifted by the TCK input. 4. Return to Run-Test/Idle. 5. Select the DR Scan path. 6. In Capture-DR: The Data on the external pins are sampled into the boundary-scan chain. 7. In Shift-DR: The boundary-scan chain is shifted by the TCK input. 8. Return to Run-Test/Idle. Table 8-6. 8.7.14.
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ATSAM4L8/L4/L2 8.7.14.4 CLAMP This instruction selects the Bypass register as Data Register. The device output pins are driven from the boundary-scan chain. Starting in Run-Test/Idle, the CLAMP instruction is accessed the following way: 1. Select the IR Scan path. 2. In Capture-IR: The IR output value is latched into the shift register. 3. In Shift-IR: The instruction register is shifted by the TCK input. 4. In Update-IR: The data from the boundary-scan chain is applied to the output pins. 5.
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ATSAM4L8/L4/L2 8.8 System Manager Access Port (SMAP) Rev.: 1.0.0.0 8.8.1 Features • • • • • 8.8.2 Chip Erase command and status Cortex-M4 core reset source 32-bit Cyclic Redundancy check of any memory accessible through the bus matrix Unlimited Flash User page read access Chip identification register Overview The SMAP provides memory-related services and also Cortex-M4 core reset control to a debugger through the Debug Port. This makes possible to halt the CPU and program the device after reset. 8.8.
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ATSAM4L8/L4/L2 8.8.6 Security Considerations In protected state this module may access sensible information located in the device memories. To avoid any risk of sensible data extraction from the module registers, all operations are non interruptible except by a disable command triggered by writing a one to CR.DIS. Issuing this command clears all the interface and internal registers.
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ATSAM4L8/L4/L2 8.8.9 Unlimited Flash User Page Read Access The SMAP can access the User page even if the protected state is set. Prior to operate such an access, the user should check that the module is not busy by checking that SR.STATE is equal to zerp. Once the offset of the word to access inside the page is written in ADDR.ADDR, the read operation can be initiated by writing a one in CR.FSPR. The SR.STATE field will indicate the FSPR state. Addresses written to ADDR.ADDR must be world aligned.
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ATSAM4L8/L4/L2 8.8.11 SMAP User Interface Table 8-9.
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ATSAM4L8/L4/L2 8.8.11.1 Name: Control Register CR Access Type: Write-Only Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - CE FSPR CRC DIS EN Writing a zero to a bit in this register has no effect.
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ATSAM4L8/L4/L2 8.8.11.
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ATSAM4L8/L4/L2 0: No bus error has been detected sincle last clear of this bit • HCR: Hold Core reset 1: The Cortex-M4 core is held under reset 0: The Cortex-M4 core is not held under reset • DONE: Operation done 1: At least one operation has terminated since last clear of this field 0: No operation has terminated since last clear of this field 82 42023E–SAM–07/2013
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ATSAM4L8/L4/L2 8.8.11.3 Name: Status Clear Register SCR Access Type: Write-Only Offset: 0x08 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - LCK FAIL BERR HCR DONE Writing a zero to a bit in this register has no effect.
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ATSAM4L8/L4/L2 8.8.11.
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ATSAM4L8/L4/L2 8.8.11.
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ATSAM4L8/L4/L2 8.8.11.
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ATSAM4L8/L4/L2 8.8.11.7 Name: Module Version VERSION Access Type: Read-Only Offset: 0x28 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 1 0 VARIANT 11 10 VERSION 3 2 VERSION • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
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ATSAM4L8/L4/L2 8.8.11.8 Name: Chip Identification Register CIDR Access Type: Read-Only Offset: 0xF0 Reset Value: - 31 30 29 EXT 23 28 27 NVPTYP 22 21 20 19 18 24 17 16 9 8 1 0 SRAMSIZ 14 13 12 11 10 NVPSIZ2 7 25 ARCH ARCH 15 26 6 NVPSIZ 5 EPROC 4 3 2 VERSION Note: Refer to section CHIPID for more information on this register.
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ATSAM4L8/L4/L2 8.8.11.9 Name: Chip Identification Extension Register EXID Access Type: Read-Only Offset: 0xF4 Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 EXID 23 22 21 20 EXID 15 14 13 12 EXID 7 6 5 4 EXID Note: Refer to section CHIPID for more information on this register.
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ATSAM4L8/L4/L2 8.8.11.
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ATSAM4L8/L4/L2 8.9 AHB-AP Access Port The AHB-AP is a Memory Access Port (MEM-AP) as defined in the ARM Debug Interface v5 Architecture Specification. The AHB-AP provides access to all memory and registers in the system, including processor registers through the System Control Space (SCS). System access is independent of the processor status. Either SW-DP or SWJ-DP is used to access the AHB-AP. The AHB-AP is a master into the Bus Matrix.
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ATSAM4L8/L4/L2 8.10 Available Features in Protected State Table 8-10.
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ATSAM4L8/L4/L2 8.11 8.11.1 Functional Description Debug Environment Figure 8-8 shows a complete debug environment example. The SWJ-DP interface is used for standard debugging functions, such as downloading code and single-stepping through the program and viewing core and peripheral registers. Figure 8-8. Application Debug Environment Example Host Debugger PC SWJ-DP Emulator/Probe SWJ-DP Connector SAM4 SAM4-based Application Board 8.11.
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ATSAM4L8/L4/L2 Figure 8-9. Application Test Environment Example Test Adaptor Tester JTAG Probe JTAG Connector SAM4 Chip n Chip 2 Chip 1 SAM4-based Application Board In Test 8.11.3 How to Initialize Test and Debug Features To enable the JTAG pins a falling edge event must be detected on the TCK pin at any time after the RESET_N pin is released. In some specific cases, the user would prevent system from running code after reset is released.
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ATSAM4L8/L4/L2 Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is latched onto the parallel output from the shift register path in the Update-IR state. The Exit-IR, Pause-IR, and Exit2-IR states are only used for navigating the state machine. Figure 8-10. Scanning in JTAG Instruction TCK TAP State TLR RTI SelDR SelIR CapIR ShIR Ex1IR UpdIR RTI TMS TDI TDO 8.11.5.
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ATSAM4L8/L4/L2 instruction for the first time. SAMPLE/PRELOAD can also be used for taking a snapshot of the external pins during normal operation of the part. When using the JTAG interface for Boundary-Scan, the JTAG TCK clock is independent of the internal chip clock, which is not required to run. NOTE: For pins connected to 5V lines care should be taken to not drive the pins to a logic one using boundary scan, as this will create a current flowing from the 3,3V driver to the 5V pullup on the line.
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ATSAM4L8/L4/L2 8.11.8 Chip Erase Typical Procedure The chip erase operation is triggered by writing a one in the CE bit in the Control Register (CR.CE). This clears first all volatile memories in the system and second the whole flash array. Note that the User page is not erased in this process. To ensure that the chip erase operation is completed, check the DONE bit in the Status Register (SR.DONE).
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ATSAM4L8/L4/L2 9. Chip Identifier (CHIPID) 9.1 Description Chip Identifier registers permit recognition of the device and its revision. These registers provide the sizes and types of the on-chip memories, as well as the set of embedded peripherals. Two chip identifier registers are embedded: CIDR (Chip ID Register) and EXID (Extension ID). Both registers contain a hard-wired value that is read-only.
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ATSAM4L8/L4/L2 Table 9-1.
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ATSAM4L8/L4/L2 9.3 User Interface Table 9-2.
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ATSAM4L8/L4/L2 9.3.1 Name: Chip ID Register CIDR Access: Read-only Offset: 0x0 Reset Value: - 31 30 29 EXT 23 28 27 26 NVPTYP 22 21 14 20 19 18 13 6 17 16 9 8 1 0 SRAMSIZ 12 11 10 NVPSIZ2 7 24 ARCH[7:4] ARCH[3:0] 15 25 NVPSIZ 5 4 3 EPROC 2 VERSION • EXT: Extension Flag 0 = Chip ID has a single register definition without extension 1 = An extended Chip ID exists.
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ATSAM4L8/L4/L2 • ARCH: Architecture Identifier Value Name Description 0x19 AT91SAM9xx AT91SAM9xx Series 0x29 AT91SAM9XExx AT91SAM9XExx Series 0x34 AT91x34 AT91x34 Series 0x37 CAP7 CAP7 Series 0x39 CAP9 CAP9 Series 0x3B CAP11 CAP11 Series 0x40 AT91x40 AT91x40 Series 0x42 AT91x42 AT91x42 Series 0x55 AT91x55 AT91x55 Series 0x60 AT91SAM7Axx AT91SAM7Axx Series 0x61 AT91SAM7AQxx AT91SAM7AQxx Series 0x63 AT91x63 AT91x63 Series 0x70 AT91SAM7Sxx AT91SAM7Sxx Series 0x71 AT9
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ATSAM4L8/L4/L2 Value Name Description 0x93 SAM3NxA SAM3NxA Series (48-pin version) 0x94 SAM3NxB SAM3NxB Series (64-pin version) 0x95 SAM3NxC SAM3NxC Series (100-pin version) 0x99 SAM3SDxB SAM3SDxB Series (64-pin version) 0x9A SAM3SDxC SAM3SDxC Series (100-pin version) 0xA5 SAM5A SAM5A 0xB0 SAM4L SAM4Lxx Series 0xF0 AT75Cxx AT75Cxx Series • SRAMSIZ: Internal SRAM Size Value Name Description 0 48K 48K bytes 1 1K 1K bytes 2 2K 2K bytes 3 6K 6K bytes 4 24K 24K bytes
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ATSAM4L8/L4/L2 • NVPSIZ2: Second Nonvolatile Program Memory Size Value Name Description 0 NONE None 1 8K 8K bytes 2 16K 16K bytes 3 32K 32K bytes 4 5 Reserved 64K 6 7 64K bytes Reserved 128K 8 128K bytes Reserved 9 256K 256K bytes 10 512K 512K bytes 11 12 Reserved 1024K 13 14 1024K bytes Reserved 2048K 15 2048K bytes Reserved • EPROC: Embedded Processor Value Name Description 1 ARM946ES ARM946ES 2 ARM7TDMI ARM7TDMI 3 CM3 Cortex-M3 4 ARM920T ARM920T 5 ARM9
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ATSAM4L8/L4/L2 Value Name 4 5 Reserved 64K 6 7 Description 64K bytes Reserved 128K 8 128K bytes Reserved 9 256K 256K bytes 10 512K 512K bytes 11 12 Reserved 1024K 13 14 1024K bytes Reserved 2048K 15 2048K bytes Reserved • VERSION: Version of the Device Current version of the device.
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ATSAM4L8/L4/L2 9.3.
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ATSAM4L8/L4/L2 • USB: USB Option Value Description 0 USB is not implemented 1 USB is implemented • USBFULL: USB Configuration Value Description 0 USB is Device-only 1 USB is Device and Host • AES: AES Option Value Description 0 AES is not implemented 1 AES is implemented Page 42023E–SAM–07/2013
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ATSAM4L8/L4/L2 10. Power Manager (PM) Rev: 4.4.1.1 10.1 Features • • • • 10.2 Generates clocks and resets for digital logic On-the-fly frequency change of CPU, HSB and PBx clocks Module-level clock gating through maskable peripheral clocks Controls resets of the device Overview The Power Manager (PM) provides synchronous clocks used to clock the main digital logic in the device, namely the CPU, and the modules and peripherals connected to the High Speed Bus (AHB) and the Peripheral Buses (APBx).
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ATSAM4L8/L4/L2 10.4 I/O Lines Description Table 10-1. I/O Lines Description Name Description Type Active Level RESET_N Reset Input Low 10.5 10.5.1 Product Dependencies Interrupt The PM interrupt line is connected to one of the internal sources of the NVIC. Using the PM interrupt requires the NVIC to be programmed first. 10.5.2 Clock Implementation In ATSAM4L, the AHB shares the source clock with the CPU. The clock for the PM bus interface (CLK_PM) is generated by the Power Manager.
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ATSAM4L8/L4/L2 Figure 10-2. Synchronous Clock Generation Power Save Mode BPM 0 Main Clock Mask 1 Main Clock Sources AHB Clocks Prescaler CPUMASK CPUDIV MCSEL CPU Clocks APBx Clocks CPUSEL 10.6.1.1 Selecting the Main Clock Source The common main clock can be connected to RCSYS or a set of other clock sources. For details about the other main clock sources, refer to Section 10.7.1 ”Main Clock Control” on page 116. By default, the main clock will be connected to RCSYS.
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ATSAM4L8/L4/L2 10.6.1.3 Clock Ready Flag There is a slight delay from CPUSEL and PBxSEL being written to the new clock setting taking effect. During this interval, the Clock Ready bit in the Status Register (SR.CKRDY) will read as zero. When the clock settings change is completed, the bit will read as one. The Clock Select registers (CPUSEL, PBxSEL) must not be written to while SR.CKRDY is zero, or the system may become unstable or hang. The Clock Ready bit in the Interrupt Status Register (ISR.
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ATSAM4L8/L4/L2 10.6.3 Speeding-up Sleep Modes Wake Up Times The normal way for the Power Manager to enter WAIT mode involves automatically switching the main clock to RCSYS before stopping all oscillators. During wake-up, the main clock is automatically switched back from RCSYS to the oscillator selected before the WFI instruction was executed. The delay needed to switch to/from the RCSYS oscillator is around three RCSYS clock cycles, plus oscillator startup times when waking up.
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ATSAM4L8/L4/L2 Depending on the reset source, when a Reset occurs, some parts of the device are not always reset. Only the Power On Reset (POR) will force a whole device reset. Refer to the table in the Module Configuration section at the end of this chapter for further details. The latest reset cause can be read in the RCAUSE register, and can be read during the applications boot sequence in order to determine proper action.
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ATSAM4L8/L4/L2 ager will generate an interrupt request if at least one of the bits in the Interrupt Mask Register (IMR) is set. Bits in IMR are set by writing a one to the corresponding bit in the Interrupt Enable Register (IER), and cleared by writing a one to the corresponding bit in the Interrupt Disable Register (IDR).
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ATSAM4L8/L4/L2 10.7 User Interface Table 10-3.
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ATSAM4L8/L4/L2 10.7.1 Name: Main Clock Control MCCTRL Access Type: Read/Write Offset: 0x000 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - MCSEL • MCSEL: Main Clock Select Table 10-4. Note: Main clocks in ATSAM4L.
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ATSAM4L8/L4/L2 10.7.2 Name: CPU Clock Select CPUSEL Access Type: Read/Write Offset: 0x004 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 CPUDIV - - - - CPUSEL • CPUDIV, CPUSEL: CPU Division and Clock Select CPUDIV = 0: CPU clock equals main clock. CPUDIV = 1: CPU clock equals main clock divided by 2(CPUSEL+1).
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ATSAM4L8/L4/L2 10.7.3 Name: PBx Clock Select PBxSEL Access Type: Read/Write Offset: 0x00C-0x018 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 PBDIV - - - - PBSEL • PBDIV, PBSEL: PBx Division and Clock Select PBDIV = 0: APBx clock equals main clock. PBDIV = 1: APBx clock equals main clock divided by 2(PBSEL+1).
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ATSAM4L8/L4/L2 10.7.4 Name: Clock Mask CPUMASK/HSBMASK/PBAMASK/PBBMASK/PBCMASK/PBDMASK Access Type: Read/Write Offset: 0x020-0x034 Reset Value: 0x00000001/0x000001E2/0x00000000/0x00000001/0x0000001F/0x0000003F- 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 MASK[31:24] 23 22 21 20 MASK[23:16] 15 14 13 12 MASK[15:8] 7 6 5 4 MASK[7:0] • MASK: Clock Mask If bit n is cleared, the clock for module n is stopped.
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ATSAM4L8/L4/L2 Table 10-5. Maskable Module Clocks in ATSAM4L.
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ATSAM4L8/L4/L2 10.7.5 Name: Divided Clock Mask PBADIVMASK Access Type: Read/Write Offset: 0x040 Reset Value: 0x0000007F 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - MASK[6:0] • MASK: Clock Mask If bit n is written to zero, the clock divided by 2(n+1) is stopped.
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ATSAM4L8/L4/L2 10.7.6 Name: Clock Failure Detector Control Register CFDCTRL Access Type: Read/Write Offset: 0x054 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 SFV - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - CFDEN • SFV: Store Final Value 0: The register is read/write. 1: The register is read-only, to protect against further accidental writes.
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ATSAM4L8/L4/L2 10.7.7 Name: PM Unlock Register UNLOCK Access Type: Write-Only Offset: 0x058 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - 7 6 5 4 3 2 ADDR[9:8] 1 0 ADDR[7:0] To unlock a write protected register, first write to the UNLOCK register with the address of the register to unlock in the ADDR field and 0xAA in the KEY field.
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ATSAM4L8/L4/L2 10.7.8 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x0C0 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - WAKE 7 6 5 4 3 2 1 0 - - CKRDY - - - - CFD Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
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ATSAM4L8/L4/L2 10.7.9 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x0C4 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - WAKE 7 6 5 4 3 2 1 0 - - CKRDY - - - - CFD Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
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ATSAM4L8/L4/L2 10.7.10 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x0C8 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - WAKE 7 6 5 4 3 2 1 0 - - CKRDY - - - - CFD 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. This bit is cleared when the corresponding bit in IDR is written to one.
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ATSAM4L8/L4/L2 10.7.11 Name: Interrupt Status Register ISR Access Type: Read-only Offset: 0x0CC Reset Value: 0x00000000 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - WAKE 7 6 5 4 3 2 1 0 - - CKRDY - - - - CFD 0: The corresponding interrupt is cleared. 1: The corresponding interrupt is pending. This bit is cleared when the corresponding bit in ICR is written to one.
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ATSAM4L8/L4/L2 10.7.12 Name: Interrupt Clear Register ICR Access Type: Write-only Offset: 0x0D0 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - WAKE 7 6 5 4 3 2 1 0 - - CKRDY - - - - CFD Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in ISR.
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ATSAM4L8/L4/L2 10.7.13 Name: Status Register SR Access Type: Read-only Offset: 0x0D4 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - WAKE 7 6 5 4 3 2 1 0 - - CKRDY - - - - CFD • AE: Access Error 0: No access error has occurred. 1: A write to lock protected register without unlocking it has occurred. • WAKE: Wake up 0: No wakeup has occurred.
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ATSAM4L8/L4/L2 10.7.14 Name: Peripheral Power Control Register PPCR Access Type: Read/Write Offset: 0x160 Reset Value: 0x000001FE 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 PPC[31:24] 23 22 21 20 PPC[23:16] 15 14 13 12 PPC[15:8] 7 6 5 4 PPC[7:0] Table 10-7.
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ATSAM4L8/L4/L2 • VREGRCMASK: VREG Request Clock Mask 0: VREG Request Clock is disabled 1: VREG Request Clock is enabled • ADCIFERCMASK: ADCIFE Request Clock Mask 0: ADCIFE Request Clock is disabled 1: ADCIFE Request Clock is enabled • PEVCRCMASK: PEVC Request Clock Mask 0: PEVC Request Clock is disabled 1: PEVC Request Clock is enabled • TWIS1RCMASK: TWIS1 Request Clock Mask 0: TWIS1 Request Clock is disabled 1: TWIS1 Request Clock is enabled • TWIS0RCMASK: TWIS0 Request Clock Mask 0: TWIS0 Request Clock is
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ATSAM4L8/L4/L2 10.7.15 Name: Reset Cause RCAUSE Access Type: Read-only Offset: 0x180 Reset Value: Latest Reset Source 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - BOD33 - - POR33 - OCDRST 7 6 5 4 3 2 1 0 - BKUP - - WDT EXT BOD POR • BOD33: Brown-out 3.3V Reset This bit is set when the last reset was due to the supply voltage being lower than the BOD 3.
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ATSAM4L8/L4/L2 10.7.16 Name: Wake Cause Register WCAUSE Access Type: Read-only Offset: 0x184 Reset Value: Latest Wake Source 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 WCAUSE[31:24] 23 22 21 20 19 WCAUSE[23:16] 15 14 13 12 11 WCAUSE[15:8] 7 6 5 4 3 WCAUSE[7:0] A bit in this register is set on wake up caused by the peripheral referred to in Table 10-8 on page 133. Table 10-8.
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ATSAM4L8/L4/L2 10.7.17 Name: Asynchronous Wake Up Enable Register AWEN Access Type: Read/Write Offset: 0x188 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 AWEN[31:24] 23 22 21 20 AWEN[23:16] 15 14 13 12 AWEN[15:8] 7 6 5 4 AWEN[7:0] Each bit in this register corresponds to an asynchronous wake up, according to Table 10-9 on page 134. 0: The corresponding wake up is disabled. 1: The corresponding wake up is enabled Table 10-9.
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ATSAM4L8/L4/L2 10.7.
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ATSAM4L8/L4/L2 10.7.19 Name: Configuration Register CONFIG Access Type: Read-Only Offset: 0x3F8 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 HSBPEVC - - - PBD PBC PBB PBA This register shows the configuration of the PM. • HSBPEVC: HSB PEVC Clock Implemented 0: HSBPEVC not implemented. 1: HSBPEVC implemented.
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ATSAM4L8/L4/L2 10.7.20 Name: Version Register VERSION Access Type: Read-Only Offset: 0x3FC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
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ATSAM4L8/L4/L2 10.8 Module Configuration The specific configuration for each PM instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Refer to the “Synchronous Clocks”, “Peripheral Clock Masking” sections for details. Table 10-10. Power Manager Clocks Clock Name Description CLK_PM Clock for the PM bus interface Table 10-11. Register Reset Values Register Reset Value VERSION 0x00000441 Table 10-12.
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ATSAM4L8/L4/L2 11. Backup Power Manager (BPM) Rev: 1.2.0.5 11.1 Features • • • • • 11.2 Supports the Power Scaling Technique Controls the Power Save Modes Manages I/O lines pin muxing for Backup mode Manages I/O lines retention in Backup mode Stores the wake up source from Backup mode Overview The Backup Power Manager (BPM) located in the Backup domain is an extension of the Power Manager (PM) module. To optimize power consumption, the BPM supports the Power Scaling Technique.
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ATSAM4L8/L4/L2 11.3 Block Diagram Figure 11-1. BPM Block Diagram Backup dom ain Cortex-M 4 W FI instruction Power Scaling Voltage Regulator PM CON Configuration VREG IF PM BPM State M achine CLK_BPM RCAUSE Power Save M odes BPM interrupt NVIC User Interface BKUPMUX PB Bus BKUPW CAUSE Backup EIC Pins I/O Line M anagem ent W AKE UP M anagem ent G PIO Controller BPM Standard EIC Pins EIC 11.
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ATSAM4L8/L4/L2 11.4.2 Interrupts The BPM interrupt line is connected to the NVIC. Using the BPM interrupt requires the NVIC to be programmed first. 11.4.3 Debug Operation If a BACKUP mode is requested by the system while in debug mode, the core domain is kept to those in RUN mode, and the debug modules are kept running to allow the debugger to access internal registers. When exiting the BACKUP mode upon a wakeup event, all the core domain is reset but the debug session.
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ATSAM4L8/L4/L2 Figure 11-2. I/O Lines Pin Muxing Diagram Backup domain User Interface BKUPMUX Backup EIC pins M U X External Interrupt Controller GPIO Controller EIC pins To enable the backup pin muxing, the user should set a one to the corresponding bit of the Backup Pin Muxing register (BKUPPMUX) in the BPM. The backup alternate function overrides the GPIO function. To allow the system to be waken up by an external interrupt pin in backup mode, the backup pin muxing should be enabled. 11.5.
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ATSAM4L8/L4/L2 11.5.6 Precautions When Entering Power Save Mode. Modules communicating with external circuits should be disabled before entering a Power Save Mode that will stop the module operation. This prevents erratic behavior when entering or exiting Power Save Mode. Refer to the relevant module documentation for recommended actions. Communication between the synchronous clock domains is disturbed when entering and exiting Power Save Modes.
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ATSAM4L8/L4/L2 11.6 User Interface Table 11-1.
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ATSAM4L8/L4/L2 11.6.1 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x0000 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - PSOK Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
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ATSAM4L8/L4/L2 11.6.2 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x0004 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - PSOK Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
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ATSAM4L8/L4/L2 11.6.3 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x0008 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - PSOK 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. This bit is cleared when the corresponding bit in IDR is written to one.
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ATSAM4L8/L4/L2 11.6.4 Name: Interrupt Status Register ISR Access Type: Read-only Offset: 0x000C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - PSOK 0: The corresponding interrupt is cleared. 1: The corresponding interrupt is pending. This bit is cleared when the corresponding bit in ICR is written to one.
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ATSAM4L8/L4/L2 11.6.5 Name: Interrupt Clear Register ICR Access Type: Write-only Offset: 0x0010 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - PSOK Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in ISR.
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ATSAM4L8/L4/L2 11.6.6 Name: Status Register SR Access Type: Read-only Offset: 0x0014 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - PSOK • AE: Access Error 0: No access error has occured. 1: A write to lock protected register without unlocking it has occured.
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ATSAM4L8/L4/L2 11.6.7 Name: Unlock Register UNLOCK Access Type: Write-Only Offset: 0x018 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - 7 6 5 4 3 2 ADDR[9:8] 1 0 ADDR[7:0] To unlock a write protected register, first write to the UNLOCK register with the address of the register to unlock in the ADDR field and 0xAA in the KEY field.
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ATSAM4L8/L4/L2 11.6.8 Name: Power Mode Control Register PMCON Access Type: Read/Write Offset: 0x001C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - FASTWKUP 23 22 21 20 19 18 17 16 - - - - - - - CK32S 15 14 13 12 11 10 9 8 - - RET BKUP 3 2 1 0 - SLEEP 7 6 5 4 - - - - PSCREQ PS • FASTWKUP: Fast Wakeup 0: Normal wakeup time for analog modules. 1: Fast wakeup time for analog modules.
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ATSAM4L8/L4/L2 1: the Power Save Mode will be the RETENTION mode if the SCR.SLEEPDEEP bit is set to 1 and the Backup Mode is set to zero. • BKUP: BACKUP Mode 0: the Power Save Mode will not be the BACKUP mode. 1: the Power Save Mode will be the BACKUP mode if the SCR.SLEEPDEEP bit is set to 1. • PSCREQ: Power Scaling Change Request 0: A new power scaling is not requested. 1: A new power scaling is requested. This bit is cleared by hardware after the completion of the power scaling change.
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ATSAM4L8/L4/L2 11.6.9 Name: Backup Wake up Cause Register BKUPWCAUSE Access Type: Read-only Offset: 0x0028 Reset Value: Latest Wake up Source from Backup mode 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 BKUPWC[31:24] 23 22 21 20 19 BKUPWC[23:16] 15 14 13 12 11 BKUPWC[15:8] 7 6 5 4 3 BKUPWC[7:0] A bit in this register is set when the system is waking up from the Backup mode and the wake up source is caused by the peripheral referred to in Table 11-3 on page 154.
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ATSAM4L8/L4/L2 11.6.10 Name: Backup Wake up Enable Register BKUPWEN Access Type: Read/Write Offset: 0x002C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 BKUPWEN[31:24] 23 22 21 20 19 BKUPWEN[23:16] 15 14 13 12 11 BKUPWEN[15:8] 7 6 5 4 3 BKUPWEN[7:0] Each bit in this register corresponds to a wake up cause from the Backup mode, according to Table 11-3 on page 154. 0: The corresponding wake up source is disabled.
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ATSAM4L8/L4/L2 11.6.11 Name: Backup Pin Muxing Register BKUPPMUX Access Type: Read/Write Offset: 0x0030 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - BKUPPMUX[8] 7 6 5 4 3 2 1 0 BKUPPMUX[7:0] • BKUPPMUX: Backup Pin Muxing Map a peripheral function required in Backup mode to a dedicated pad.
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ATSAM4L8/L4/L2 11.6.12 Name: Input Output Retention Register IORET Access Type: Read/Write Offset: 0x0034 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - RET • RET: Retention on I/O lines after waking up from the BACKUP mode 0: I/O lines are not held after waking up from the BACKUP mode.
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ATSAM4L8/L4/L2 11.6.13 Name: Version Register VERSION Access Type: Read-Only Offset: 0x00FC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
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ATSAM4L8/L4/L2 11.7 Module Configuration The specific configuration for each BPM instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Refer to the “Synchronous Clocks”, “Peripheral Clock Masking” and “Power Save Modes” sections for details. Table 11-6. Power Manager Clocks Clock Name Description CLK_BPM Clock for the BPM bus interface Table 11-7.
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ATSAM4L8/L4/L2 12. Backup System Control Interface (BSCIF) Rev: 1.0.0.0 12.1 Features • Supports 32KHz ultra-low-power oscillator (OSC32K) •Supports 32kHz RC oscillator (RC32K) • Supports 1MHz RC oscillator (RC1M) • Controls Brown-out detectors (BOD18 and BOD33) • Controls the Voltage Regulation System • Four 32-bit general-purpose backup registers 12.2 Overview The Backup System Control Interface (BSCIF) controls the oscillators, BODs, Voltage Regulation System and Backup Registers.
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ATSAM4L8/L4/L2 12.3 Block Diagram Figure 12-1. BSCIF Block Diagram Reset Controller APB BUS NVIC Voltage Regulation System BANDGAP BACKUP REGISTERS VOLTAGE REGULATOR RC1M BACKUP SYSTEM CONTROL INTERFACE (BSCIF) BOD18 BOD33 WATCHDOG TIMER RC32K ASYNCHRONOUS TIMER XIN32 OSC32K XOUT32 PMCON.CK32S (from BPM) BACKUP DOMAIN 12.4 I/O Lines Description Table 12-1.
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ATSAM4L8/L4/L2 12.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 12.5.1 Power Management The 32 kHz oscillators (RC32K and OSC32K) are not turned off in Power Save modes. BODs are turned off in some Power Save modes and turned automatically on when the device wakes up. The Voltage Regulation System is controlled by the BPM, refer to Section 11. ”Backup Power Manager (BPM)” on page 139 for details. 12.5.
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ATSAM4L8/L4/L2 ated on a zero-to-one transition on PCLKSR.OSC32RDY if the OSC32RDY bit in the Interrupt Mask Register (IMR.OSC32RDY) is set. This bit is set by writing a one to the corresponding bit in the Interrupt Enable Register (IER.OSC32RDY). As a crystal oscillator usually requires a very long start-up time (up to 1 second), the 32 KHz oscillator will keep running across resets, except a Power-on Reset (POR).
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ATSAM4L8/L4/L2 If the reference clock stops when the RC32K is in closed loop mode, the RC32K Reference Error bit (PCLKSR.RC32KREFE) is set, and the RC32K stays in closed loop mode, keeping the current FINE value. When the reference clock starts again, the RC32K automatically resumes the tracking of the reference clock. In closed loop mode, if the correct frequency is out of range for the FINE value, it will saturate due to an incorrect COARSE setting. The RC32K Saturation bit (PCLKSR.
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ATSAM4L8/L4/L2 Figure 12-2. BOD18/33 Block Diagram VDDANA VDDCORE BOD18 Reset BOD18 Level BOD18 Hyst Oneshot mode Cont mode BOD18 Detected BOD33 Reset BOD18 BOD33 Level BOD33 Hyst Oneshot mode Cont mode BOD33 Detected BOD33 POWER MANAGER (PM) Interrupt Reset SCIF BSCIF NVIC The BOD18/33 is enabled by writing a one to the Enable bit in the BOD18/33 Control Register (BOD18/33CTRL.EN).
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ATSAM4L8/L4/L2 12.6.3.3 Continuous Mode When BOD18/33CTRL.MODE is zero, the BOD18/33 operates in continuous mode. In continuous mode the BOD18/33 is enabled and continously monitoring the supply voltage. The continuos mode is the default mode. 12.6.3.
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ATSAM4L8/L4/L2 • RCSYS: This oscillator is always enabled when selected as clock source. Refer to Section 10. ”Power Manager (PM)” on page 108 for details about RCSYS and the Power Save Modes. Refer to the Section 42.7 ”Oscillator Characteristics” on page 1142 chapter for the oscillator’s frequency characteristics. • OSC32K or RC32K: This oscillator has to be enabled in the BSCIF Interface before using it as clock source for the BOD18/33. The BOD18/33 will not be able to detect if this clock is stopped.
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ATSAM4L8/L4/L2 12.6.3.11 Power Save Modes In continuous mode the BOD18/33 will be off during WAIT, RETENTION and BACKUP Power Save Modes. In sampling mode the BOD18/33 is enabled in all Power Save Modes. Table 12-2. 12.6.3.
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ATSAM4L8/L4/L2 12.6.4.2 12.6.5 1MHz RC Oscillator The 1MHz RC Oscillator which is used for switching regulator operation can also be internally routed to be used as a logic clock. This oscillator is controlled by the RC1MCR register. Its startup calibration value is read from flash fuses. Bandgap Rev: 1.1.0.7 The Bandgap provides a stable voltage reference used by the internally by the device. This reference is automatically turned on at startup.
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ATSAM4L8/L4/L2 • BOD33DET - Brown out 3.3 Detected: – Set on 0 to 1 transition on the PCLKSR.BOD33DET bit is detected. • RC32KSAT- RC32K FINE value saturated: – 0: The RC32K autocalibration has not saturated the FINE value. – 1: The RC32K autocalibration has brought FINE into saturation. • RC32KREFE - RC32K Reference error: – 0: The RC32K has detected a running reference frequency. – 1: The RC32K reference frequency has stopped.
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ATSAM4L8/L4/L2 12.7 User Interface Table 12-3.
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ATSAM4L8/L4/L2 12.7.1 Interrupt Enable Register Name: IER Access Type: Write-only Offset: 0x0000 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - LPBGRDY - VREGOK SSWRDY BOD18SYN RDY 7 6 5 4 3 2 1 0 BOD33SYN RDY BOD18DET BOD33DET RC32SAT RC32KREFE RC32KLOCK RC32KRDY OSC32RDY Writing a zero to a bit in this register has no effect.
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ATSAM4L8/L4/L2 12.7.2 Interrupt Disable Register Name: IDR Access Type: Write-only Offset: 0x0004 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - LPBGRDY - VREGOK SSWRDY BOD18SYN RDY 7 6 5 4 3 2 1 0 BOD33SYN RDY BOD18DET BOD33DET RC32SAT RC32KREFE RC32KLOCK RC32KRDY OSC32RDY Writing a zero to a bit in this register has no effect.
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ATSAM4L8/L4/L2 12.7.3 Interrupt Mask Register Name: IMR Access Type: Read-only Offset: 0x0008 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - LPBGRDY - VREGOK SSWRDY BOD18SYN RDY 7 6 5 4 3 2 1 0 BOD33SYN RDY BOD18DET BOD33DET RC32SAT RC32KREFE RC32KLOCK RC32KRDY OSC32RDY 0: The corresponding interrupt is disabled.
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ATSAM4L8/L4/L2 12.7.4 Interrupt Status Register Name: ISR Access Type: Read-only Offset: 0x000C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - LPBGRDY - VREGOK SSWRDY BOD18SYN RDY 7 6 5 4 3 2 1 0 BOD33SYN RDY BOD18DET BOD33DET RC32SAT RC32KREFE RC32KLOCK RC32KRDY OSC32RDY 0: The corresponding interrupt is cleared.
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ATSAM4L8/L4/L2 12.7.5 Interrupt Clear Register Name: ICR Access Type: Write-only Offset: 0x0010 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - LPBGRDY - VREGOK SSWRDY BOD18SYN RDY 7 6 5 4 3 2 1 0 BOD33SYN RDY BOD18DET BOD33DET RC32SAT RC32KREFE RC32KLOCK RC32KRDY OSC32RDY Writing a zero to a bit in this register has no effect.
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ATSAM4L8/L4/L2 12.7.6 Power and Clocks Status Register Name: PCLKSR Access Type: Read-only Offset: 0x0014 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - LPBGRDY RC1MRDY VREGOK SSWRDY BOD18SYN RDY 7 6 5 4 3 2 1 0 BOD33SYN RDY BOD18DET BOD33DET RC32SAT RC32KREFE RC32KLOCK RC32KRDY OSC32RDY • LPBGRDY: 0: Low Power Bandgap not enabled or not ready.
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ATSAM4L8/L4/L2 1: The RC32K autocalibration has brought FINE into saturation. • RC32KREFE: 0: The RC32K has detected a running reference frequency. 1: The RC32K reference frequency has stopped. • RC32KLOCK: 0: The RC32K has not obtained a lock to the reference frequency. 1: The RC32K has obtained alock to the reference frequency. • RC32KRDY: 0: Reads from FINE and COARSE will yield invalid values.
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ATSAM4L8/L4/L2 12.7.7 Unlock Register Name: UNLOCK Access Type: Write-only Offset: 0x0018 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - 7 6 5 4 3 2 ADDR[9:8] 1 0 ADDR[7:0] To unlock a write protected register, first write to the UNLOCK register with the address of the register to unlock in the ADDR field and 0xAA in the KEY field.
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ATSAM4L8/L4/L2 12.7.8 32KHz Oscillator Control Register Name: OSCCTRL32 Access Type: Read/Write Reset Value: 0x00000004 31 30 29 28 27 26 25 24 RESERVED - - - - - - - 23 22 21 20 19 18 17 16 - - - - - 15 14 13 12 11 SELCURR[3:0] STARTUP[2:0] 10 - 9 8 MODE[2:0] 7 6 5 4 3 2 1 0 - - - - EN1K EN32K - OSC32EN Note: This register is only reset by Power-On Reset • RESERVED This bit must always be written to zero.
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ATSAM4L8/L4/L2 Select current driven into the crystal. Table 12-5. Crystal Current selection SELCURR Current Value (nA) 0 50 1 75 2 100 3 125 4 150 5 175 6 200 7 225 8 250 9 275 10 300 (recommended value) 11 325 12 350 13 375 14 400 15 425 • MODE: Oscillator Mode Table 12-6. MODE Operation Mode for 32 KHz Oscillator Description 0 External clock connected to XIN32 1 Crystal mode. Crystal is connected to XIN32/XOUT32.
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ATSAM4L8/L4/L2 1: The 32 KHz Oscillator is enabled 182 42023E–SAM–07/2013
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ATSAM4L8/L4/L2 12.7.9 32 KHz RC Oscillator Control Register Name: RC32KCR Access Type: Read/Write Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 FCD - REF MODE EN1K EN32K TCEN EN • FCD: Flash calibration done Signifies that COARSE in the RC32KCALIB register has been loaded with value from fuses. 0: Fuses not loaded.
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ATSAM4L8/L4/L2 12.7.10 RC32K Tuning Register Name: RC32KTUNE Access Type: Read/Write Reset Value: 0x002C0020 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - COARSE[4:0] 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - FINE[5:0] • COARSE: Coarse Value The offset value for FINE. • FINE: Fine value The fine calibration value.
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ATSAM4L8/L4/L2 12.7.11 Name: BOD Control Register BOD18/33CTRL Access Type: Read/Write Reset Value: - 31 30 29 28 27 26 25 24 SFV FCD - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - MODE 15 14 13 12 11 10 9 8 - - - - - - 7 6 5 4 3 2 1 0 - - - - - - HYST EN ACTION • SFV: BOD Control Register Store Final Value 0: BOD Control Register is not locked. 1: BOD Control Register is locked.
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ATSAM4L8/L4/L2 • EN: Enable 0: The BOD is disabled. 1: The BOD is enabled.
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ATSAM4L8/L4/L2 12.7.12 Name: BOD Sampling Control Register BOD18/33SAMPLING Access Type: Read/Write Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - 7 6 5 4 3 2 1 0 - - - - - - CSSEL CEN PSEL[3:0] • PSEL: Prescaler Select Select the prescaler divide-by output for the BOD Sampling mode. • CSSEL: Clock Source Select 0: Selects the RCSYS as BOD Sampling clock source.
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ATSAM4L8/L4/L2 12.7.13 Name: BOD Level Register BOD18/33LEVEL Access Type: Read/Write Reset Value: 0x00000000 31 30 29 28 27 26 25 24 RANGE - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - VAL[5:0] • RANGE: BOD Threshold Range (available for BOD18 only) 0: The Standard Threshold Range is selected. See Section 42.9 ”Analog Characteristics” on page 1150 for actual voltage levels.
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ATSAM4L8/L4/L2 12.7.14 Voltage Regulator Configuration Register Name: VREGCR Access Type: Read/Write Reset Value: - 31 30 29 28 27 26 25 24 SFV - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - SSWEVT SSW SSG 7 6 5 4 3 2 1 0 - - - - - - - DIS • SFV: Store Final Value 0: The DIS field is read/write. 1: The DIS field is read-only, to protect against further accidental writes.
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ATSAM4L8/L4/L2 12.7.15 1MHz RC Clock Configuration Register Name: RC1MCR Access Type: Read/Write Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - 7 6 5 4 3 2 1 0 FCD - - - - - - CLKOEN CLKCAL[4:0] • CLKCAL: 1MHz RC Osc Calibration Calibration field of the internal RC oscillator. • CLKOEN: 1MHz RC Osc Clock Output Enable 0: The 1MHz RC oscillator is not output.
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ATSAM4L8/L4/L2 12.7.16 Name: Bandgap Control Register BGCTRL Access Type: Read/Write Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - TSEN 7 6 5 4 3 2 1 0 - - - - - - ADCISEL • ADCISEL: ADC Input Selection 0: no connection. 1: Reserved. 2: ADC is connected to the voltage reference. 3: Reserved.
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ATSAM4L8/L4/L2 12.7.17 Name: Bandgap Status Register BGSR Access Type: Read Only Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - LPBGRDY BGRDY 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 VREF BGBUFRDY[7:0] • VREF: Voltage Reference Used by the System 0: Both the Bandgap voltage reference and the Low Power Bandgap voltage reference are currently used by the system.
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ATSAM4L8/L4/L2 12.7.18 Backup Register n Name: BRn Access Type: Read/Write Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DATA[31:24] 23 22 21 20 DATA[23:16] 15 14 13 12 DATA[15:8] 7 6 5 4 DATA[7:0] This is a set of general-purpose read/write registers. Data stored in these registers is retained when the device is in BACKUP Power Save Mode. Note that this registers are protected by a lock.
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ATSAM4L8/L4/L2 12.7.19 Name: Backup Register Interface Version Register BRIFBVERSION Access Type: Read-only Offset: 0x03E4 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
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ATSAM4L8/L4/L2 12.7.20 Bandgap Reference Interface Version Register Name: BGREFIFBVERSION Access Type: Read-only Offset: 0x03E8 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
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ATSAM4L8/L4/L2 12.7.21 Voltage Regulator Version Register Name: VREGIFGVERSION Access Type: Read-only Offset: 0x03EC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
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ATSAM4L8/L4/L2 12.7.22 Brown-Out Detector Version Register Name: BODIFCVERSION Access Type: Read-only Offset: 0x03F0 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
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ATSAM4L8/L4/L2 12.7.23 32kHz RC Oscillator Version Register Name: RC32KIFBVERSION Access Type: Read-only Offset: 0x03F4 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
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ATSAM4L8/L4/L2 12.7.24 32kHz Oscillator Version Register Name: OSC32IFAVERSION Access Type: Read-only Offset: 0x03F8 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
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ATSAM4L8/L4/L2 12.7.25 BSCIF Version Register Name: VERSION Access Type: Read-only Offset: 0x03FC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:0] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
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ATSAM4L8/L4/L2 12.8 Module Configuration The specific configuration for each BSCIF instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Refer to Section 10. ”Power Manager (PM)” on page 108 for details. Table 12-8. MODULE Clock Name Module Name Clock Name Description BSCIF CLK_BSCIF Clock for the BSCIF bus interface Table 12-9.
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ATSAM4L8/L4/L2 13. System Control Interface (SCIF) Rev: 1.3.0.0 13.1 Features • • • • • • • 13.2 Supports crystal oscillator 0.
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ATSAM4L8/L4/L2 13.4 I/O Lines Description Table 13-1. 13.5 I/O Lines Description Pin Name Pin Description Type XIN Crystal Input Analog/Digital XOUT Crystal Output Analog GCLK3-GCLK0 Generic Clock Output Output GCLK_IN1-GCLK_IN0 Generic Clock Input Input Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 13.5.
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ATSAM4L8/L4/L2 The oscillator is disabled by default after reset. When the oscillator is disabled, the XIN and XOUT pins can be used as general purpose I/Os. When the oscillator is enabled, the XIN and XOUT pins are controlled directly by the SCIF, overriding GPIO settings. When the oscillator is configured to use an external clock, the clock must be applied to the XIN pin while the XOUT pin can be used as general purpose I/O.
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ATSAM4L8/L4/L2 Figure 13-2. PLL with Control Logic and Filters PLLMUL PLLOPT[1] fvco Output Divider 0 1/2 fREF Source clocks PLLOSC 13.6.2.1 Input Divider PLLDIV Phase Detector VCO Lock Counter fPLL Mask PLL clock 1 Lock bit PLLOPT[0] Enabling the PLL Before the PLL is enabled it must be set up correctly. The PLL Oscillator Select field (PLLOSC) selects a source for the reference clock.
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ATSAM4L8/L4/L2 13.6.3 Digital Frequency Locked Loop (DFLL) Operation Rev.: 1.1.0.0 The number of DFLLs is device specific. A specific DFLL is referred to as DFLLx, where x can be any number from 0 to n, where n refers to the last DFLL instance. Refer to the module configuration section for details. The DFLLx is controlled by the corresponding DFLLx registers. DFLLx is disabled by default, but can be enabled to provide a high-frequency source clock for synchronous and generic clocks.
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ATSAM4L8/L4/L2 13.6.3.1 Enabling the DFLL DFLLx is enabled by writing a one to the Enable bit in the DFLLx Configuration Register (DFLLxCONF.EN). No other bits or fields in DFLLxCONF must be changed simultaneously, or before DFLLx is enabled. 13.6.3.2 Internal Synchronization Due to multiple clock domains, values in the DFLLx configuration registers need to be synchronized to other clock domains. The status of this synchronization can be read from the Power and Clocks Status Register (PCLKSR).
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ATSAM4L8/L4/L2 in open loop mode is to first configure it for closed loop mode, see Section 13.6.3.5. When a lock is achieved, read back the COARSE and FINE values and switch to open loop mode using these values. An alternative approach is to use the Frequency Meter (FREQM) to monitor the DFLL frequency and adjust the COARSE and FINE values based on measurement results form the FREQM. Refer to the FREQM chapter for more information on how to use it.
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ATSAM4L8/L4/L2 Writing to DFLLxMUL.MUL while in closed loop mode will reset the locks. FINE will be set to half its maximum value and the full locking sequence will be restarted. Frequency locking The locking of the frequency in closed loop mode is divided into two stages. In the COARSE stage the control logic quickly finds the correct value for DFLLxVAL.COARSE and thereby sets the output frequency to a value close to the correct frequency. The DFLLx Locked on Coarse Value bit in PCLKSR (PCLKSR.
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ATSAM4L8/L4/L2 If a one is written to DFLLxCONF.STABLE, DFLLxVAL.FINE will never change after Fine Lock is set. The frequency will be measured and the error value can be read from the DFLLxRATIO.RATIODIFF. It is possible to change the value of DFLLxCONF.STABLE while in lock, without loosing the locks. This enables the user to let the DFLLx compensate for drift if DFLLxRATIO.RATIODIFF is too big, and having a stable frequency when this is required.
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ATSAM4L8/L4/L2 The generic clock CLK_DFLLx_SSG must be configured and enabled before SSG is enabled, refer to Generic Clocks section for details. This clock sets the rate at which the SSG changes the frequency of the DFLL clock to generate a spread spectrum. The frequency of this clock should be higher than fCLK_DFLLx_REF to ensure that the DFLLx can lock. Optionally, the clock ticks can be qualified by a Pseudo Random Binary Sequence (PRBS) if the PRBS bit in DFLLxSSG is one (DFLLxSSG.PRBS).
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ATSAM4L8/L4/L2 DFLLxCONF.LLAW is one when going to a Power Save Mode where the DFLLx is turned off, the DFLLx will lose all its locks when waking up, and needs to regain these through the full lock sequence. 13.6.3.9 Accuracy There are mainly three factors that decide the accuracy of the fCLK_DFLLx. These can be tuned to obtain maximum accuracy when fine lock is achieved. • FINE resolution: The frequency step between two FINE values. This is relatively smaller for high output frequencies.
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ATSAM4L8/L4/L2 After a Power-On Reset (POR), the Calibration field (RCFASTCFG.CALIB) is loaded with a factory-defined value stored in the Flash fuses. The Flash Calibration Done bit (RCFASTCFG.FCD) is set when RCFASTCFG.CALIB has been loaded from flash. For testing purposes, it is possible to override the default fuse values by writing to the RCFASTCFG.CALIB field. To prevent unexpected frequency change, the RCFAST must be disabled before modifying the CALIB field.
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ATSAM4L8/L4/L2 Register (RCFASTCFG). The FRANGE and CALIB fields should only be updated when the RCFAST is disabled. Since this is in open loop mode, the frequency will be voltage, temperature, and process dependent. Refer to Section 42. ”Electrical Characteristics” on page 1120 for details. 13.6.5.4 Closed Loop Mode If the tuner is enabled (RCFASTCFG.TUNEEN is one), the RCFAST is in closed loop mode.
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ATSAM4L8/L4/L2 To prevent unexpected writes due to software bugs, write access to the RC80MCR register is protected by a locking mechanism. For details refer to Section 13.7.7 ”Unlock Register” on page 228. The RC80M is automatically switched off in certain sleep modes to reduce power consumption, as described in Section 10. ”Power Manager (PM)” on page 108. 13.6.7 Generic Clock Prescalers Rev: 1.0.2.
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ATSAM4L8/L4/L2 Figure 13-9. Fractional Prescaler Generation Divider CKSEL FPMUL FPDIV Mask FPCLK FPEN The FP is enabled by writing a one to the FPEN bit in the Fractional Prescaler Control Register (FPCR). The user can select a clock source for the FP by writing to the CKSEL field of the FPCR register. The user must configure the FP frequency by writing to the FPMUL and FPDIV fields of the FPMUL and FPDIV registers.
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ATSAM4L8/L4/L2 Timers, communication modules, and other modules connected to external circuitry may require specific clock frequencies to operate correctly. The SCIF defines a number of generic clocks that can provide a wide range of accurate clock frequencies. Each generic clock runs from either clock source listed in the “Generic Clock Sources” table in the SCIF Module Configuration section. The selected source can optionally be divided by any even integer up to 512.
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ATSAM4L8/L4/L2 13.6.8.4 13.6.9 Generic Clock Allocation The generic clocks are allocated to different functions as shown in the “Generic Clock Allocation” table in the SCIF Module Configuration section. Interrupts The SCIF has the following interrupt sources: • AE - Access Error: – A protected SCIF register was accessed without first being correctly unlocked. • RCFASTLOCKLOST - RCFASTLock Lost – A to 1 transition on the PCLKSR.RCFASTLOCKLOST bit is detected.
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ATSAM4L8/L4/L2 13.7 User Interface Table 13-3.
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ATSAM4L8/L4/L2 Table 13-3.
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ATSAM4L8/L4/L2 13.7.1 Interrupt Enable Register Name: IER Access Type: Write-only Offset: 0x0000 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - 11 10 9 8 - - - - - 15 14 13 12 - RCFASTLOC KLOST RCFASTLOC K - 7 6 5 4 3 2 1 0 PLL0LOCKL OST PLL0LOCK - DFLL0RCS DFLL0RDY DFLL0LOCK F DFLL0LOCK C OSC0RDY Writing a zero to a bit in this register has no effect.
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ATSAM4L8/L4/L2 13.7.2 Interrupt Disable Register Name: IDR Access Type: Write-only Offset: 0x0004 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - RCFASTLOC KLOST RCFASTLOC K - - - - - 7 6 5 4 3 2 1 0 PLL0LOCKL OST PLL0LOCK - DFLL0RCS DFLL0RDY DFLL0LOCK F DFLL0LOCK C OSC0RDY Writing a zero to a bit in this register has no effect.
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ATSAM4L8/L4/L2 13.7.3 Interrupt Mask Register Name: IMR Access Type: Read-only Offset: 0x0008 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - RCFASTLOC KLOST RCFASTLOC K - - - - - 7 6 5 4 3 2 1 0 PLL0LOCKL OST PLL0LOCK - DFLL0RCS DFLL0RDY DFLL0LOCK F DFLL0LOCK C OSC0RDY 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
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ATSAM4L8/L4/L2 13.7.4 Interrupt Status Register Name: ISR Access Type: Read-only Offset: 0x000C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - RCFASTLOC KLOST RCFASTLOC K - - - - - 7 6 5 4 3 2 1 0 PLL0LOCKL OST PLL0LOCK - DFLL0RCS DFLL0RDY DFLL0LOCK F DFLL0LOCK C OSC0RDY 0: The corresponding interrupt is cleared.
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ATSAM4L8/L4/L2 13.7.5 Interrupt Clear Register Name: ICR Access Type: Write-only Offset: 0x0010 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - RCFASTLOC KLOST RCFASTLOC K - - - - - 7 6 5 4 3 2 1 0 PLL0LOCKL OST PLL0LOCK - DFLL0RCS DFLL0RDY DFLL0LOCK F DFLL0LOCK C OSC0RDY Writing a zero to a bit in this register has no effect.
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ATSAM4L8/L4/L2 13.7.
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ATSAM4L8/L4/L2 1: DFLL is locked on Coarse value, and is ready to be selected as clock source with medium accuracy on the output clock. • OSC0RDY: OSC0 Ready 0: Oscillator not enabled or not ready. 1: Oscillator is stable and ready to be used as clock source.
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ATSAM4L8/L4/L2 13.7.7 Unlock Register Name: UNLOCK Access Type: Write-only Offset: 0x0018 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - 7 6 5 4 3 2 ADDR[9:8] 1 0 ADDR[7:0] To unlock a write protected register, first write to the UNLOCK register with the address of the register to unlock in the ADDR field and 0xAA in the KEY field.
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ATSAM4L8/L4/L2 13.7.8 Oscillator Control Register Name: OSCCTRLn Access Type: Read/Write Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - OSCEN 15 14 13 12 11 10 9 8 - - - - 7 6 5 4 1 0 - - - STARTUP[3:0] 3 AGC 2 GAIN[1:0] MODE • OSCEN: Oscillator Enable 0: The oscillator is disabled. 1: The oscillator is enabled. • STARTUP: Oscillator Start-up Time Select start-up time for the oscillator.
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ATSAM4L8/L4/L2 13.7.9 Name: PLL Control Register PLLn Access Type: Read/Write Reset Value: 0x00000000 31 30 29 28 - - 23 22 21 20 - - - - 15 14 13 12 - - - - 7 6 5 4 - - 27 26 25 24 18 17 16 9 8 1 0 PLLCOUNT PLLOPT 19 PLLMUL 11 10 PLLDIV 3 2 PLLOSC PLLEN • PLLCOUNT: PLL Count Specifies the number of RCSYS clock cycles before ISR.PLLLOCKn will be set after PLLn has been written, or after PLLn has been automatically re-enabled after exiting a sleep mode.
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ATSAM4L8/L4/L2 • PLLEN: PLL Enable 0: PLL is disabled. 1: PLL is enabled. Note that it is not possible to change any of the PLL configuration bits when the PLL is enabled, Any write to PLLn while the PLL is enabled will be discarded. Note that this register is protected by a lock. To write to this register the UNLOCK register has to be written first. Refer to Section 13.7.7 ”Unlock Register” on page 228 for details.
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ATSAM4L8/L4/L2 13.7.10 Name: DFLLx Configuration Register DFLLxCONF Access Type: Read/Write Reset Value: 0x0X100000(1) Note: 31 30 29 28 27 26 25 24 - - - - 23 22 21 20 19 18 17 16 FCD - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - QLDIS CCDIS - LLAW STABLE MODE EN CALIB RANGE 1. The reset value of CALB depends on factory calibration. • CALIB: Calibration Value Sets the Calibration Value for the DFLLx.
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ATSAM4L8/L4/L2 13.7.11 DFLLx Value Register Name: DFLLxVAL Access Type: Read/Write Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 COARSE FINE • COARSE: Coarse Value Set the value of the coarse calibration register. In closed loop mode, this field is read-only. • FINE: Fine value Set the value of the fine calibration register.
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ATSAM4L8/L4/L2 13.7.12 DFLLx Multiplier Register Name: DFLLxMUL Access Type: Read/Write Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 MUL[15:8] 7 6 5 4 MUL[7:0] • MUL: DFLL Multiply Factor This field determines the ratio of the CLK_DFLLx output frequency to the CLK_DFLLx_REF input frequency. Note that this register is protected by a lock.
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ATSAM4L8/L4/L2 13.7.13 DFLLx Maximum Step Register Name: DFLLxSTEP Access Type: Read/Write Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 CSTEP FSTEP • CSTEP: Coarse Maximum Step This indicates the maximum step size during coarse adjustment in closed loop mode.
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ATSAM4L8/L4/L2 13.7.14 DFLLx Spread Spectrum Generator Control Register Name: DFLLxSSG Access Type: Read/Write Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - 15 14 13 9 8 - - - 7 6 5 4 3 2 1 0 - - - - - - PRBS EN STEPSIZE 12 11 10 AMPLITUDE • STEPSIZE: SSG Step Size Selects the step size of the spread spectrum.
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ATSAM4L8/L4/L2 13.7.15 DFLLx Ratio Register Name: DFLLxRATIO Access Type: Read-only Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 2 1 0 RATIODIFF[15:8] 7 6 5 4 3 RATIODIFF[7:0] • RATIODIFF: Multiplication Ratio Difference In closed loop mode, this field indicates the error in the ratio between the CLK_DFLLx frequency and the target frequency.
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ATSAM4L8/L4/L2 13.7.16 DFLLx Synchronization Register Name: DFLLxSYNC Access Type: Write-only Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - SYNC • SYNC: Synchronization To be able to read the current value of DFLLxVAL or DFLLxRATIO, this bit must be written to one.
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ATSAM4L8/L4/L2 13.7.17 System RC Oscillator Calibration Register Name: RCCR Access Type: Read/Write Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - FCD 15 14 13 12 11 10 9 8 - - - - - - 7 6 5 4 3 2 CALIB[9:8] 1 0 CALIB[7:0] • FCD: Flash Calibration Done 0: The flash calibration will be redone after any reset. 1: The flash calibration will only be redone after a Power-on Reset.
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ATSAM4L8/L4/L2 13.7.18 Name: 4/8/12MHz RC Oscillator Configuration Register RCFASTCFG Access Type: Read/Write Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 11 10 9 8 - - 3 2 1 0 - JITMODE TUNEEN EN 15 CALIB 14 13 12 LOCKMARGIN 7 FCD 6 5 NBPERIODS 4 FRANGE • CALIB: Oscillator Calibration Value Writing a value to this field sets the oscillator trim value.
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ATSAM4L8/L4/L2 1: The RCFAST clock is enabled, and the output clock is running. Note that this register is protected by a lock. To write to this register the UNLOCK register has to be written first. Refer to Section 13.7.7 ”Unlock Register” on page 228 for details.
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ATSAM4L8/L4/L2 13.7.19 Name: 4/8/12MHz RC Oscillator Status Register RCFASTSR Access Type: Read-only Reset Value: 0x00000000 31 30 29 28 27 26 25 24 UPDATED - - - - - LOCKLOST LOST 23 22 21 20 19 18 17 16 - - SIGN 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - CNTERR CURTRIM • UPDATED: Current Trim Value Updated This field toggles each time the tuning procedure completes.
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ATSAM4L8/L4/L2 13.7.20 80MHz RC Oscillator Control Register Name: RC80MCR Access Type: Read/Write Reset Value: 0x00000000 31 30 29 28 27 26 - - - - - - 23 22 21 20 19 18 - - - - - - 15 14 13 12 11 10 - - - - - - 7 6 5 4 3 - - FCD 25 24 17 16 CALIB 9 8 2 1 0 - - EN • CALIB: Calibration Value Calibration Value for the RC oscillator (read-only). • FCD: Flash Calibration Done • EN: Enable 0: The oscillator is disabled. 1: The oscillator is enabled.
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ATSAM4L8/L4/L2 13.7.21 High Resolution Prescaler Control Register Name: HRPCR Access Type: Read/Write Reset Value: 0x00000000 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 HRCOUNT[23:16] 23 22 21 20 19 HRCOUNT[15:8] 15 14 13 12 11 HRCOUNT[7:0] 7 6 5 4 - - - - 3 CKSEL HRPEN • HRCOUNT: High Resolution Counter Specify the input clock period to count to generate the output clock edge.
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ATSAM4L8/L4/L2 13.7.22 Fractional Prescaler Control Register Name: FPCR Access Type: Read/Write Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - CKSEL FPEN • CKSEL: Clock input selection This field selects the Clock input for the prescaler.
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ATSAM4L8/L4/L2 13.7.23 Fractional Prescaler Mul Register Name: FPMUL Access Type: Read/Write Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 FPMUL[15:8] 7 6 5 4 FPMUL[7:0] • FPMUL: Fractional Prescaler Multiplication Factor This field selects the multiplication factor for the prescaler. Notice that FPMUL is always smaller than FPDIV.
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ATSAM4L8/L4/L2 13.7.24 Fractional Prescaler Div Register Name: FPDIV Access Type: Read/Write Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 FPDIV[15:8] 7 6 5 4 FPDIV[7:0] • FPDIV: Fractional Prescaler Division Factor This field selects the division factor for the prescaler. Notice that FPMUL must be smaller than FPDIV.
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ATSAM4L8/L4/L2 13.7.25 Generic Clock Control Name: GCCTRL Access Type: Read/Write Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 DIV[15:8] 23 22 21 20 DIV[7:0] 15 14 13 12 - - - 7 6 5 4 3 2 1 0 - - - - - - DIVEN CEN OSCSEL[4:0] There is one GCCTRL register per generic clock in the design.
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ATSAM4L8/L4/L2 13.7.26 Name: 4/8/12MHz RC Oscillator Version Register RCFASTVERSION Access Type: Read-only Offset: 0x03D8 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
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ATSAM4L8/L4/L2 13.7.27 Generic Clock Prescalers Version Register Name: GCLKPRESCVERSION Access Type: Read-only Offset: 0x03DC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
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ATSAM4L8/L4/L2 13.7.28 PLL Version Register Name: PLLIFAVERSION Access Type: Read-only Offset: 0x03E0 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
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ATSAM4L8/L4/L2 13.7.29 Oscillator 0 Version Register Name: OSCIFAVERSION Access Type: Read-only Offset: 0x03E4 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
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ATSAM4L8/L4/L2 13.7.30 Digital Frequency Locked Loop Version Register Name: DFLLIFBVERSION Access Type: Read-only Offset: 0x03E8 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
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ATSAM4L8/L4/L2 13.7.31 RC Oscillator Version Register Name: RCOSCIFAVERSION Access Type: Read-only Offset: 0x03EC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
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ATSAM4L8/L4/L2 13.7.32 80MHz RC Oscillator Version Register Name: RC80MVERSION Access Type: Read-only Offset: 0x03F4 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
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ATSAM4L8/L4/L2 13.7.33 Generic Clock Version Register Name: GCLKIFVERSION Access Type: Read-only Offset: 0x03F8 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
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ATSAM4L8/L4/L2 13.7.34 SCIF Version Register Name: VERSION Access Type: Read-only Offset: 0x03FC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:0] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
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ATSAM4L8/L4/L2 13.8 Module Configuration The specific configuration for each SCIF instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Refer to Section 10. ”Power Manager (PM)” on page 108 for details. Table 13-4. SCIF Clock Name Module Name Clock Name Description SCIF CLK_SCIF Clock for the SCIF bus interface Table 13-5.
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ATSAM4L8/L4/L2 In ATSAM4L8/L4/L2, there are 12 generic clocks. These are allocated to different functions as shown in Table 13-7. Table 13-7.
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ATSAM4L8/L4/L2 Table 13-8. Generic Clock Sources OSCSEL Clock/Oscillator Description 15 CLK_1K 1kHz output clock from OSC32K 16 PLL0 Output clock from PLL0 17 HRP High Resolution Prescaler Output 18 FP Fractionnal Prescaler Output 19-20 GCLK_IN[0-1] GCLK_IN[0-1] pins, digital clock input 21 GCLK11 Generic Clock 11. Can not be use as input to itself. 22-31 Reserved . Table 13-9.
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ATSAM4L8/L4/L2 Table 13-11. HRP and FP Clock Sources CKSEL Clock/Oscillator Description 0 OSC0 Output clock from Oscillator0 1 PLL0 Output clock from PLL0 2 DFLL0 Output clock from DFLL0 3 reserved 4 RC80M Output from 80MHz RCOSC Table 13-12.
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ATSAM4L8/L4/L2 14. Flash Controller (FLASHCALW) Rev: 1.1.0.1 14.1 Features • • • • • • • • • • • 14.
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ATSAM4L8/L4/L2 Block Diagram PicoCache enabled Cortex-M 4 Cortex-M 4 I/D AHB System AHB PicoCache disabled I/D AHB 14.3 PicoCache 2 KB RAM HRAMC1 256 KB FLASH 14.4 HM ATRIX FLASH Controller FLASH Controller HMATRIX PicoCache 2 KB RAM 256 KB FLASH Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 14.4.
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ATSAM4L8/L4/L2 and that CLK_FLASHCALW_APB is not turned off before accessing the FLASHCALW configuration and control registers. Failing to do so may deadlock the bus. 14.4.3 Interrupts The FLASHCALW interrupt request lines are connected to the NVIC. Using the FLASHCALW interrupts requires that it is programmed first. 14.4.4 Debug Operation When an external debugger forces the CPU into debug mode, the FLASHCALW continues normal operation.
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ATSAM4L8/L4/L2 14.5 14.5.1 Functional Description Bus Interfaces The FLASHCALW has three bus interfaces, two High Speed Bus (HSB) interfaces for: – reads from the flash memory and writes to the page buffer – read/write in the PicoCache internal RAM when it is disabled and one Peripheral Bus (PB) interface for issuing commands and reading status from the controller.
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ATSAM4L8/L4/L2 14.5.2 Flash Memory Organization The flash memory is divided into a set of pages. A page is the basic unit addressed when programming the flash. A page consists of several words. The pages are grouped into 16 regions of equal size. _AHBEach of these regions can be locked by a dedicated fuse bit, protecting it from accidental modification.
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ATSAM4L8/L4/L2 undefined result. The User page is permanently mapped to an offset of 0x00800000 from the start address of the flash memory. Table 14-1. User Page Addresses Memory type Start address, byte sized Size Main array 0 pw bytes User 0x00800000 w bytes Figure 14-1.
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ATSAM4L8/L4/L2 Figure 14-2. Memory Map for the Flash Memories Offset from base address Reserved User Page Reserved 0x0080 0000 Flash data array pw 0 Flash base address Flash with User Page All addresses are byte addresses 14.5.5 High Speed Read Mode The flash provides a High Speed Read Mode, offering slightly higher flash read speed at the cost of higher power consumption. Two dedicated commands, High Speed Read Mode Enable (HSEN) and High Speed Read Mode Disable (HSDIS) control the speed mode.
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ATSAM4L8/L4/L2 Figure 14-3. High Speed Mode Frequency 1 wait state 0 wait state Frequency limit for 0 wait state operation Speed mode H m h ig or N al 14.5.6 Quick Page Read A dedicated command, Quick Page Read (QPR), is provided to read all words in an addressed page. All bits in all words in this page are AND’ed together, returning a 1-bit result. This result is placed in the Quick Page Read Result (QPRR) bit in Flash Status Register (FSR).
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ATSAM4L8/L4/L2 14.5.8 Page Buffer Operations The flash memory has a write and erase granularity of one page; data is written and erased in chunks of one page. When programming a page, the user must first write the new data into the Page Buffer. The contents of the entire Page Buffer is copied into the desired page in flash memory when the user issues the Write Page command, Refer to Section 14.6.1 on page 275.
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ATSAM4L8/L4/L2 The page buffer is also used for writes to the User page. Page buffer write operations are performed with 4 wait states. Any accesses attempted to the FLASHCALW on the HSB bus during these cycles will be automatically stalled. Writing to the page buffer can only change page buffer bits from one to zero, i.e. writing 0xAAAAAAAA to a page buffer location that has the value 0x00000000 will not change the page buffer value.
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ATSAM4L8/L4/L2 14.5.9 14.5.9.1 PicoCache Description Overview The PicoCache is an unified direct mapped cache controller. It integrates a controller, a tag directory, a data memory, a metadata memory and a configuration interface. When it is not activated, the cache memory is accessible as a supplementary RAM connected on the bus matrix. Note that for security reasons, this memory is cleared by a chip erase operation. 14.5.9.
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ATSAM4L8/L4/L2 Cortex-M4 Memory Fault exception. When operating a chip erase, the PicoCache will be cleared whether it was enabled or not.
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ATSAM4L8/L4/L2 14.6 Flash Commands The FLASHCALW offers a command set to manage programming of the flash memory, locking and unlocking of regions, and full flash erasing. See Section 14.10.2 for a complete list of commands. To run a command, the CMD field in the Flash Command Register (FCMD) has to be written with the command number. As soon as the FCMD register is written, the FRDY bit in the Flash Status Register (FSR) is automatically cleared. Once the current command is complete, the FSR.
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ATSAM4L8/L4/L2 14.6.1 Write/Erase Page Operation Flash technology requires that an erase must be done before programming. The entire flash can be erased by an Erase All command. Alternatively, pages can be individually erased by the Erase Page command. The User page can be written and erased using the mechanisms described in this chapter. After programming, the page can be locked to prevent miscellaneous write or erase sequences.
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ATSAM4L8/L4/L2 When the command is complete, the FRDY bit in the Flash Status Register (FSR) is set. If an interrupt has been enabled by writing FCR.FRDY to one, an interrupt request is generated. Two errors can be detected in the FSR register after issuing the command: • Programming Error: A bad keyword and/or an invalid command have been written in the FCMD register. • Lock Error: At least one lock region is protected. The erase command has been aborted and no page has been erased.
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ATSAM4L8/L4/L2 • PAGEN[10:3] - Fuse value to write All general-purpose fuses can be erased by the Erase All General-Purpose fuses (EAGP) command. An EAGP command is not allowed if the flash is locked by the security fuses. Two errors can be detected in the FSR register after issuing these commands: • Programming Error: A bad keyword and/or an invalid command have been written in the FCMD register. • Lock Error: The lock bits are implemented using the lowest 16 general-purpose fuse bits.
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ATSAM4L8/L4/L2 Figure 14-5.
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ATSAM4L8/L4/L2 14.10 User Interface Table 14-3.
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ATSAM4L8/L4/L2 14.10.1 Name: Flash Control Register FCR Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - reserved 7 6 5 4 3 2 1 0 WS1OPT FWS - -ECCE PROGE LOCKE - FRDY • reserved: Must be 0.
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ATSAM4L8/L4/L2 14.10.2 Name: Flash Command Register FCMD Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 The FCMD can not be written if the flash is in the process of performing a flash command. Doing so will cause the FCR write to be ignored, and the PROGE bit in FSR to be set.
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ATSAM4L8/L4/L2 Table 14-4. Semantic of PAGEN field in different commands Command PAGEN description Program GP Fuse Byte WriteData[7:0], ByteAddress[2:0] Erase All GP Fuses Not used Quick Page Read Page number Write User Page Not used Erase User Page Not used Quick Page Read User Page Not used High Speed Mode Enable Not used High Speed Mode Disable Not used • CMD: Command This field defines the flash command.
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ATSAM4L8/L4/L2 14.10.
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ATSAM4L8/L4/L2 14.10.4 Name: Flash Parameter Register FPR Access Type: Read-only Offset: 0x0C Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - 7 6 5 4 3 - - - - PSZ 2 1 0 FSZ • PSZ: Page Size The size of each flash page. Table 14-6.
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ATSAM4L8/L4/L2 • FSZ: Flash Size The size of the flash. Not all device families will provide all flash sizes indicated in the table. Table 14-7.
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ATSAM4L8/L4/L2 14.10.5 Name: Flash Version Register FVR Access Type: Read-only Offset: 0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
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ATSAM4L8/L4/L2 14.10.
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ATSAM4L8/L4/L2 14.10.
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ATSAM4L8/L4/L2 14.10.
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ATSAM4L8/L4/L2 14.10.9 Name: PicoCache Status Register SR Access Type: Read-only Offset: 0x40C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - CSTS • CSTS: Cache Controller Status 0: When read as 0, this field indicates that the cache controller is disabled.
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ATSAM4L8/L4/L2 14.10.10 PicoCache Maintenance Register 0 Name: MAINT0 Access Type: Write-only Offset: 0x420 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - INVALL • INVALL: Cache Controller Invalidate All 0: no effect. 1: When set to one, this field invalidate all cache entries.
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ATSAM4L8/L4/L2 14.10.11 PicoCache Maintenance Register 1 Name: MAINT1 Access Type: Write-only Offset: 0x424 Reset Value: 0x00000000 31 30 reserved 29 28 27 26 25 24 - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - INDEX • reserved: must be null.
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ATSAM4L8/L4/L2 14.10.
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ATSAM4L8/L4/L2 14.10.
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ATSAM4L8/L4/L2 14.10.
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ATSAM4L8/L4/L2 14.10.
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ATSAM4L8/L4/L2 14.10.
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ATSAM4L8/L4/L2 14.11 Fuse Settings The flash contains 32 general purpose fuses. These 32 fuses can be found in the Flash General Purpose Fuse Register Low (FGPFRLO). The Flash General Purpose Fuse Register High (FGPFRHI) is not used. In addition to the general purpose fuses, parts of the flash user page can have a defined meaning outside of the flash controller and will also be described in this section.
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ATSAM4L8/L4/L2 14.11.1 Flash General Purpose Fuse Register Low (FGPFRLO) 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 LOCK[15:8] 7 6 5 4 LOCK[7:0] Default Fuse Value: The devices are shipped with the FGPFRLO register value:0xFFFFFFFF: Reserved fuses set to 1. LOCK fuses set to 1111111111111111. No region locked. After the JTAG chip erase command, the FGPFR register value is 0xFFFFFFFF.
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ATSAM4L8/L4/L2 14.11.
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ATSAM4L8/L4/L2 • BOD33LEVEL: 3v3 Brown Out Detector Level This controls the voltage trigger level for the 3v3 Brown out detector. Refer to Section 42. ”Electrical Characteristics” on page 1120. • WDTAUTO: WatchDog Timer Auto Enable at Startup 0: The WDT is automatically enabled at startup. 1: The WDT is not automatically enabled at startup. Refer to the WDT chapter for detail about timeout settings when the WDT is automatically enabled.
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ATSAM4L8/L4/L2 14.11.3 Second Word of the User Page (Address 0x80800000) 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - - Default user page second word value: The devices are shipped with the User page erased (all bits 1). 14.12 Serial Number Each device has a unique 120 bits serial number readable from address 0x0080020C to 0x0080021A. 14.
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ATSAM4L8/L4/L2 The module bus clocks listed here are connected to the system bus clocks. Refer to Section 10. ”Power Manager (PM)” on page 108 for details Table 14-9. Module Name FLASHCALW Module Clock Name Clock Name Description CLK_FLASHCALW_AHB Clock for the FLASHCALW AHB interface CLK_HRAMC1_AHB Clock for the HRAMC1 interface CLK_FLASHCALW_APB Clock for the FLASHCALW PB interface Table 14-10.
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ATSAM4L8/L4/L2 15. HSB Bus Matrix (HMATRIXB) Rev: 1.3.0.3 15.1 Features • • • • • • • • • 15.
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ATSAM4L8/L4/L2 To change from one kind of default master to another, the Bus Matrix user interface provides the Slave Configuration Registers, one for each slave, that set a default master for each slave. The Slave Configuration Register contains two fields: DEFMSTR_TYPE and FIXED_DEFMSTR.
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ATSAM4L8/L4/L2 • Undefined Length Burst Arbitration In order to avoid long slave handling during undefined length bursts (INCR), the Bus Matrix provides specific logic in order to re-arbitrate before the end of the INCR transfer. A predicted end of burst is used as a defined length burst transfer and can be selected among the following five possibilities: 1. Infinite: No predicted end of burst is generated and therefore INCR burst transfer will never be broken. 2.
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ATSAM4L8/L4/L2 rent transfer, if no other master request is pending, the slave remains connected to the last master that performed the access. Other non privileged masters still get one latency cycle if they want to access the same slave. This technique can be used for masters that mainly perform single accesses. • Round-Robin Arbitration with Fixed Default Master This is another biased round-robin algorithm.
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ATSAM4L8/L4/L2 15.5 User Interface Table 15-1.
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ATSAM4L8/L4/L2 Table 15-1.
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ATSAM4L8/L4/L2 Table 15-1.
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ATSAM4L8/L4/L2 15.5.1 Name: Master Configuration Registers MCFG0...MCFG15 Access Type: Read/Write Offset: 0x00 - 0x3C Reset Value: 0x00000002 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – ULBT • ULBT: Undefined Length Burst Type Table 15-2.
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ATSAM4L8/L4/L2 15.5.2 Name: Slave Configuration Registers SCFG0...
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ATSAM4L8/L4/L2 15.5.3 Bus Matrix Priority Registers A For Slaves Register Name: PRAS0...PRAS15 Access Type: Read/Write Offset: - Reset Value: 0x00000000 31 30 - - 23 22 - - 15 14 - - 7 6 - - 29 28 M7PR 21 20 M5PR 13 12 M3PR 5 4 M1PR 27 26 - - 19 18 - - 11 10 - - 3 2 - - 25 24 M6PR 17 16 M4PR 9 8 M2PR 1 0 M0PR • MxPR: Master x Priority Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority.
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ATSAM4L8/L4/L2 15.5.4 Name: Priority Registers B For Slaves PRBS0...PRBS15 Access Type: Read/Write Offset: - Reset Value: 0x00000000 31 30 - - 23 22 - - 15 14 - - 7 6 - - 29 28 M15PR 21 20 M13PR 13 12 M11PR 5 4 M9PR 27 26 - - 19 18 - - 11 10 - - 3 2 - - 25 24 M14PR 17 16 M12PR 9 8 M10PR 1 0 M8PR • MxPR: Master x Priority Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority.
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ATSAM4L8/L4/L2 15.5.5 Name: Special Function Registers SFR0...SFR15 Access Type: Read/Write Offset: 0x110 - 0x14C Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SFR 23 22 21 20 SFR 15 14 13 12 SFR 7 6 5 4 SFR • SFR: Special Function Register Fields Those registers are not a HMATRIX specific register. The field of those will be defined where they are used.
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ATSAM4L8/L4/L2 15.6 Module Configuration The specific configuration for each HMATRIX instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Refer to Section 10. ”Power Manager (PM)” on page 108 for details. Table 15-3. 15.6.1 HMATRIX Clocks Clock Name Description CLK_HMATRIX Clock for the HMATRIX bus interface Bus Matrix Connections The bus matrix has the several masters and slaves.
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ATSAM4L8/L4/L2 Figure 15-1.
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ATSAM4L8/L4/L2 16. Peripheral DMA Controller (PDCA) Rev: 1.2.4.1 16.1 Features • • • • • 16.
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ATSAM4L8/L4/L2 16.3 Block Diagram Figure 16-1. PDCA Block Diagram Peripheral 0 Memory HSB to PB Bridge HSB Peripheral Bus HSB High Speed Bus Matrix HSB Interrupt Controller IRQ Peripheral 2 ... Peripheral DMA Controller (PDCA) Peripheral 1 Peripheral (n-1) Handshake Interfaces 16.4 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 16.4.
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ATSAM4L8/L4/L2 16.4.4 16.5 16.5.1 Peripheral Events The PDCA peripheral events are connected via the Peripheral Event System. Refer to Section 31. ”Peripheral Event Controller (PEVC)” on page 844 for details. Functional Description Basic Operation The PDCA consists of multiple independent PDCA channels, each capable of handling DMA requests in parallel. Each PDCA channels contains a set of configuration registers which must be configured to start a DMA transfer.
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ATSAM4L8/L4/L2 If TCR is zero when writing to TCRR, the TCR and MAR are automatically updated with the value written in TCRR and MARR. 16.5.5 Ring Buffer When Ring Buffer mode is enabled the TCRR and MARR registers will not be cleared when TCR and MAR registers reload. This allows the PDCA to read or write to the same memory region over and over again until the transfer is actively stopped by the user. Ring Buffer mode is enabled by writing a one to the Ring Buffer bit in the Mode Register (MR.RING). 16.
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ATSAM4L8/L4/L2 16.5.10 Priority If more than one PDCA channel is requesting transfer at a given time, the PDCA channels are prioritized by their channel number. Channels with lower numbers have priority over channels with higher numbers, giving channel zero the highest priority. 16.5.11 Error Handling If the Memory Address Register (MAR) is set to point to an invalid location in memory, an error will occur when the PDCA tries to perform a transfer.
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ATSAM4L8/L4/L2 16.6 User Interface 16.6.1 Memory Map Overview Table 16-1. PDCA Register Memory Map Address Range Contents 0x000 - 0x03F DMA channel 0 configuration registers 0x040 - 0x07F DMA channel 1 configuration registers ... ... (0x000 - 0x03F)+m*0x040 DMA channel m configuration registers 0x834 Version register The channels are mapped as shown in Table 16-1. Each channel has a set of configuration registers, shown in Table 16-2, where n is the channel number. 16.6.
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ATSAM4L8/L4/L2 16.6.4 Name: Memory Address Register MAR Access Type: Read/Write Offset: 0x000 + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 18 17 16 11 10 9 8 3 2 1 0 MADDR[31:24] 23 22 21 20 19 MADDR[23:16] 15 14 13 12 MADDR[15:8] 7 6 5 4 MADDR[7:0] • MADDR: Memory Address Address of memory buffer. MADDR should be programmed to point to the start of the memory buffer when configuring the PDCA.
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ATSAM4L8/L4/L2 16.6.5 Name: Peripheral Select Register PSR Access Type: Read/Write Offset: 0x004 + n*0x040 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 PID • PID: Peripheral Identifier The Peripheral Identifier selects which peripheral should be connected to the DMA channel.
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ATSAM4L8/L4/L2 16.6.6 Name: Transfer Counter Register TCR Access Type: Read/Write Offset: 0x008 + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 TCV[15:8] 7 6 5 4 TCV[7:0] • TCV: Transfer Counter Value Number of data items to be transferred by the PDCA. TCV must be programmed with the total number of transfers to be made.
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ATSAM4L8/L4/L2 16.6.7 Name: Memory Address Reload Register MARR Access Type: Read/Write Offset: 0x00C + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 MARV[31:24] 23 22 21 20 MARV[23:16] 15 14 13 12 MARV[15:8] 7 6 5 4 MARV[7:0] • MARV: Memory Address Reload Value Reload Value for the MAR register. This value will be loaded into MAR when TCR reaches zero if the TCRR register has a nonzero value.
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ATSAM4L8/L4/L2 16.6.8 Name: Transfer Counter Reload Register TCRR Access Type: Read/Write Offset: 0x010 + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 TCRV[15:8] 7 6 5 4 TCRV[7:0] • TCRV: Transfer Counter Reload Value Reload value for the TCR register. When TCR reaches zero, it will be reloaded with TCRV if TCRV has a positive value.
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ATSAM4L8/L4/L2 16.6.9 Name: Control Register CR Access Type: Write-only Offset: 0x014 + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - ECLR 7 6 5 4 3 2 1 0 - - - - - - TDIS TEN • ECLR: Transfer Error Clear Writing a zero to this bit has no effect. Writing a one to this bit will clear the Transfer Error bit in the Status Register (SR.
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ATSAM4L8/L4/L2 16.6.10 Name: Mode Register MR Access Type: Read/Write Offset: 0x018 + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - RING ETRIG SIZE • RING: Ring Buffer 0:The Ring buffer functionality is disabled. 1:The Ring buffer functionality is enabled.
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ATSAM4L8/L4/L2 16.6.11 Name: Status Register SR Access Type: Read-only Offset: 0x01C + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - TEN • TEN: Transfer Enabled This bit is cleared when the TDIS bit in CR is written to one. This bit is set when the TEN bit in CR is written to one.
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ATSAM4L8/L4/L2 16.6.12 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x020 + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - TERR TRC RCZ Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
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ATSAM4L8/L4/L2 16.6.13 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x024 + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - TERR TRC RCZ Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
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ATSAM4L8/L4/L2 16.6.14 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x028 + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - TERR TRC RCZ 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
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ATSAM4L8/L4/L2 16.6.15 Name: Interrupt Status Register ISR Access Type: Read-only Offset: 0x02C + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - TERR TRC RCZ • TERR: Transfer Error This bit is cleared when no transfer errors have occurred since the last write to CR.ECLR.
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ATSAM4L8/L4/L2 16.6.16 Name: PDCA Version Register VERSION Access Type: Read-only Offset: 0x834 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
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ATSAM4L8/L4/L2 16.7 Module Configuration The specific configuration for each PDCA instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Refer to Section 10. ”Power Manager (PM)” on page 108 for details. Table 16-5. PDCA Configuration Feature PDCA Number of channels 16 Number of performance monitors 0 Table 16-6.
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ATSAM4L8/L4/L2 The table below defines the valid Peripheral Identifiers (PIDs). The direction is specified as observed from the memory, so RX means transfers from peripheral to memory and TX means from memory to peripheral. Table 16-8.
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ATSAM4L8/L4/L2 Table 16-8.
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ATSAM4L8/L4/L2 17. USB Device and Embedded Host Interface (USBC) Rev: 3.1.0.19 17.1 Features • • • • • • • • • • • 17.2 Compatible with the USB 2.0 specification Supports full (12Mbit/s) and low (1.
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ATSAM4L8/L4/L2 The USBC module consists of: • HSB master interface • User interface • USB Core • Transceiver pads Figure 17-1. USBC Block Diagram GPIO Controller USB AHB APB USB_ID HSB Master DM User Interface USB 2.
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ATSAM4L8/L4/L2 17.4 I/O Lines Description Table 17-2.
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ATSAM4L8/L4/L2 17.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 17.5.1 I/O Lines The USBC pins may be multiplexed with the I/O Controller lines. The user must first configure the I/O Controller to assign the desired USBC pins to their peripheral functions. The USB VBUS and ID pin lines should be connected to GPIO pins and the user should monitor this with software. 17.5.
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ATSAM4L8/L4/L2 17.6 Functional Description 17.6.1 USB General Operation 17.6.1.1 Initialization After a hardware reset, the USBC is disabled. When enabled, the USBC runs in either device mode or in host mode according to the ID detection. The USBC Mode (USBCON.UIMOD) should be configured to set the USBC controller in either Host mode or Device mode. Figure 17-2.
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ATSAM4L8/L4/L2 17.6.1.2 Interrupts One interrupt vector is assigned to the USBC. See Section 17.6.2.19 and Section 17.6.3.16 for further details about device and host interrupts. See Section 17.5.4 for asynchronous interrupts. 17.6.1.3 Frozen clock When the USB clock is frozen, it is still possible to access the following bits: UIMOD, FRZCLK, and USBE in the USBCON register, and LS in the UDCON register. When FRZCLK is set, only the asynchronous interrupts can trigger a USB interrupt (see Section 17.5.
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ATSAM4L8/L4/L2 17.6.1.6 Pad Suspend Figure 17-4 illustrates the behavior of the USB pad in device mode. Figure 17-4. Pad Behavior USBE = 1 & DETACH = 0 & Suspend Idle USBE = 0 | DETACH = 1 | Suspend Active • In Idle state, the pad is in low power consumption mode. • In Active state, the pad is working. Figure 17-5 illustrates the pad events leading to a PAD state change. Figure 17-5.
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ATSAM4L8/L4/L2 17.6.2 17.6.2.1 USBC Device Mode Operation Device Enabling In device mode, the USBC supports full- and low-speed data transfers. Including the default control endpoint, a total of 8 endpoints are provided. They can be configured as isochronous, bulk or interrupt types, as described in Table 17-1 on page 340 After a hardware reset, the USBC device mode is in the reset state (see Section 17.6.1.1).
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ATSAM4L8/L4/L2 17.6.2.6 Busy bank enable In order to make an endpoint bank look busy regardless of its actual state, the user can write a one to the Busy Bank Enable bit in the Endpoint n Control Register (UECONnSET.BUSY0/1ES). If a BUSYnE bit is set, any transaction to this bank will be rejected with a NAK reply. 17.6.2.7 Address setup The USB device address is set up according to the USB protocol. • After all kinds of resets, the USB device address is 0.
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ATSAM4L8/L4/L2 17.6.2.10 Remote wakeup The remote wakeup request (also known as upstream resume) is the only request the device may send on its own initiative. This should be preceded by a DEVICE_REMOTE_WAKEUP request from the host. • First, the USBC must have detected a “Suspend” state on the bus, i.e. the remote wakeup request can only be sent after a SUSP interrupt has been set.
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ATSAM4L8/L4/L2 Figure 17-6.
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ATSAM4L8/L4/L2 • The control and status fields for the endpoint and bank (EPn_CTR_STA_BK0/1): Table 17-4. 31:19 EPn_CTR_STA_BK0/1 structure 18 17 16 15:1 Status elements - UNDERF OVERF 0 Control elements CRCERR - STALLRQ_NEXT – UNDERF: Underflow status for isochronous IN transfer. See ”Data flow error” on page 358. – OVERF: Overflow status for isochronous OUT transfer. See ”Data flow error” on page 358. – CRCERR: CRC error status for isochronous OUT transfer. See ”CRC error” on page 358.
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ATSAM4L8/L4/L2 17.6.2.13 Multi packet mode and single packet mode. Single packet mode is the default mode where one USB packet is managed per bank. The multi-packet mode allows the user to manage data exceeding the maximum endpoint size (UECFGn.EPSIZE) for an endpoint bank across multiple packets without software intervention. This mode can also be coupled with the ping-pong mode. • For an OUT endpoint, the EPn_PCKSIZE_BK0/1.
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ATSAM4L8/L4/L2 Figure 17-7. Control Write SETUP USB Bus DATA SETUP OUT STATUS OUT IN IN NAK RXSTPI HW SW RXOUTI HW SW HW SW TXINI SW • Control read Figure 17-8 on page 353 shows a control read transaction. The USBC has to manage the simultaneous write requests from the CPU and USB host. Figure 17-8.
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ATSAM4L8/L4/L2 17.6.2.15 Management of IN endpoints • Overview IN packets are sent by the USBC device controller upon IN requests from the host. The endpoint and its descriptor in RAM must be pre configured (see section ”RAM management” on page 349 for more details). When the current bank is clear, the TXINI and FIFO Control (UECONn.FIFOCON) bits will be set simultaneously. This triggers an EPnINT interrupt if the Transmitted IN Data Interrupt Enable (TXINE) bit in UECONn is one.
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ATSAM4L8/L4/L2 • Detailed description The data is written according to this sequence: • When the bank is empty, TXINI and FIFOCON are set, which triggers an EPnINT interrupt if TXINE is one. • The user acknowledges the interrupt by clearing TXINI. • The user reads the UESTAX.CURRBK field to see which the current bank is. • The user writes the data to the current bank, located in RAM as described by its descriptor: EPn_ADDR_BK0/1.
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ATSAM4L8/L4/L2 set, or if the total byte count is not an integral multiple of EPSIZE, whereby the last packet should be short. To enable the multi packet mode, the user should configure the endpoint descriptor (EPn_PCKSIZE_BK0/1.BYTE_COUNT) to the total size of the multi packet, which should be larger than the endpoint size (EPSIZE). Since the EPn_PCKSIZE_BK0/1.
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ATSAM4L8/L4/L2 Figure 17-13. Example of an OUT endpoint with two data banks DATA (bank 0) OUT ACK OUT DATA (bank 1) HW RXOUTI ACK HW SW SW read data from CPU BANK 0 FIFOCON SW read data from CPU BANK 1 • Detailed description Before using the OUT endpoint, one should properly initialize its descriptor for each bank. See Figure 17-6 on page 350. The data is read, according to this sequence: • When the bank is full, RXOUTI and FIFOCON are set, which triggers an EPnINT interrupt if RXOUTE is one.
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ATSAM4L8/L4/L2 • A packet has been successfully received and the updated BYTE_COUNT equals the MULTI_PACKET_SIZE. • A short packet (smaller than EPSIZE) has been received. 17.6.2.17 Data flow error This error exists only for isochronous IN/OUT endpoints. It sets the Errorflow Interrupt (ERRORFI) bit in UESTAn, which triggers an EPnINT interrupt if the Errorflow Interrupt Enable (ERRORFE) bit is one. The user can check the EPn_CTR_STA_BK0/1.
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ATSAM4L8/L4/L2 • The Start of Frame (SOF) interrupt with a frame number CRC error (FNCERR is one) • Endpoint interrupts The processing device endpoint interrupts are: • The Transmitted IN Data Interrupt (TXINI) • The Received OUT Data Interrupt (RXOUTI) • The Received SETUP Interrupt (RXSTPI) • The Number of Busy Banks (NBUSYBK) interrupt The exception device endpoint interrupts are: • The Errorflow Interrupt (ERRORFI) • The NAKed OUT Interrupt (NAKOUTI) • The NAKed IN Interrupt (NAKINI) • The STALLed Inter
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ATSAM4L8/L4/L2 17.6.3 17.6.3.1 USB Host Operation Host Enabling Figure 17-14 on page 360 describes the USBC host mode main states. Figure 17-14. Host mode states Device Disconnection Macro off Clock stopped Idle Device Connection Device Disconnection Ready SOFE = 0 SOFE = 1 Suspend After a hardware reset, the USBC host mode is in the Reset state (see Section 17.6.1.1). When the USBC is enabled (USBCON.USBE = 1) in host mode (USBCON.UIMOD = 0) it enters Idle state.
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ATSAM4L8/L4/L2 Figure 17-15. USB Communication Flow In host mode, the USBC associates a pipe to a device endpoint, according to the device configuration descriptors. 17.6.3.4 USB reset The USBC sends a USB reset signal when the user writes a one to the Send USB Reset bit (UHCON.RESET). When the USB reset has been sent, the USB Reset Sent Interrupt bit in the Host Global Interrupt register (UHINT.RSTI) is set and all the pipes will be disabled. If the bus was previously in a suspended state (UHCON.
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ATSAM4L8/L4/L2 17.6.3.7 Remote wakeup Writing UHCON.SOFE to zero when in host mode will cause the USBC to cease sending SOF’s on the USB bus and enter the Suspend state. The USB device will enter the Suspend state 3ms later. The device can awaken the host by sending an Upstream Resume (remote wakeup feature). When the host detects a non-idle state on the USB bus, it sets the Host Wakeup interrupt bit (UHINT.HWUPI).
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ATSAM4L8/L4/L2 Figure 17-16.
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ATSAM4L8/L4/L2 • The control and status fields for the pipe and bank (Pn_CTR_STA_BK0/1): Table 17-6. 31:19 Pn_CTR_STA_BK0/1 structure 18 17 16 15:0 Status - UNDERF Control OVERF CRCERR - – UNDERF: Underflow status for isochronous/Interrupt IN transfers. This status bit is set by hardware at the current bank (where the IN packet should have been stored). When a new successful transaction occurs this bit is overwritten to zero if UPSTAX.ERRORFI has previously been cleared by software.
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ATSAM4L8/L4/L2 – DTGLER: Is set if a Data toggle error occurs during a USB transaction. 17.6.3.9 Multi packet mode and single packet mode. See ”Multi packet mode and single packet mode.” on page 352 and just consider that an OUT pipe corresponds to an IN endpoint, and an IN pipe corresponds to an OUT endpoint. 17.6.3.
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ATSAM4L8/L4/L2 RXINI should always be cleared before clearing FIFOCON to avoid missing an RXINI event. Figure 17-17. Example of an IN pipe with one data bank DATA (bank 0) IN ACK IN DATA (bank 0) HW ACK HW SW RXINI SW read data from CPU BANK 0 FIFOCON read data from CPU BANK 0 SW Figure 17-18.
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ATSAM4L8/L4/L2 TXOUTI shall be cleared by software to acknowledge the interrupt. This is done by writing a one to the Transmitted OUT Data Interrupt Clear bit (UPCONnCLR.TXOUTIC), which does not affect the pipe FIFO. The user writes the OUT data to the bank referenced to by the PEPn descriptor and allows the USBC to send the data by writing a one to the FIFO Control Clear (UPCONnCLR.FIFOCONC) bit. This will also cause a switch to the next bank if the OUT pipe is composed of multiple banks.
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ATSAM4L8/L4/L2 Figure 17-21. Example of an OUT pipe with two data banks and a bank switching delay OUT DATA (bank 0) ACK OUT DATA (bank 1) ACK HW TXOUTI SW FIFOCON SW write data to CPU BANK 0 SW SW write data to CPU BANK 1 SW write data to CPU BANK0 • Multi packet mode for OUT pipes See section ”Multi packet mode for IN endpoints” on page 355 and just replace IN endpoints with OUT pipe. 17.6.3.
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ATSAM4L8/L4/L2 A CRC error can occur during the IN stage if the USBC detects a corrupted packet. The IN packet will remain stored in the bank and RXINI will be set. The user can check the Pn_CTR_STA_BK0/1.CRCERR bit in the pipe descriptor to see which current bank has been affected. 17.6.3.16 Interrupts There are two kinds of host interrupts: processing, i.e. their generation is part of the normal processing, and exception, i.e. errors not related to CPU exceptions.
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ATSAM4L8/L4/L2 17.7 User Interface Table 17-9.
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ATSAM4L8/L4/L2 Table 17-9.
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ATSAM4L8/L4/L2 17.7.1 USB General Registers 17.7.1.1 Name: General Control Register USBCON Access Type: Read/Write Offset: 0x0800 Reset Value: 0x03004000 31 30 29 28 27 26 25 24 - - - - - - UIMOD - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 11 10 9 8 USBE FRZCLK - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - - - - • UIMOD: USBC Mode 0: The module is in USB host mode. 1: The module is in USB device mode.
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ATSAM4L8/L4/L2 17.7.1.2 General Status Register Register Name: USBSTA Access Type: Read-Only Offset: 0x0804 Reset Value: 0x00010000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - SUSPEND 15 14 13 12 11 10 9 8 - CLKUSABLE - - VBUSRQ - 7 6 5 4 3 2 1 0 - - - - - - - SPEED • SUSPEND: Suspend usb transceiver state This bit is cleared when the usb transceiver is switched off.
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ATSAM4L8/L4/L2 17.7.1.3 General Status Clear Register Register Name: USBSTACLR Access Type: Write-Only Offset: 0x0808 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - VBUSRQC - 7 6 5 4 3 2 1 0 - - - - - - - - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in USBSTA.
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ATSAM4L8/L4/L2 17.7.1.4 General Status Set Register Register Name: USBSTASET Access Type: Write-Only Offset: 0x080C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - VBUSRQS - 7 6 5 4 3 2 1 0 - - - - - - - - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in USBSTA.
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ATSAM4L8/L4/L2 17.7.1.5 Version Register Register Name: UVERS Access Type: Read-Only Offset: 0x0818 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
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ATSAM4L8/L4/L2 17.7.1.
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ATSAM4L8/L4/L2 17.7.1.7 Address Size Register Register Name: UADDRSIZE Access Type: Read-Only Offset: 0x0820 Reset Value: - 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 UADDRSIZE[31:24] 23 22 21 20 19 UADDRSIZE[23:16] 15 14 13 12 11 UADDRSIZE[15:8] 7 6 5 4 3 UADDRSIZE[7:0] • UADDRSIZE: IP PB Address Size This field indicates the size of the PB address space reserved for the USBC IP interface.
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ATSAM4L8/L4/L2 17.7.1.8 IP Name Register 1 Register Name: UNAME1 Access Type: Read-Only Offset: 0x0824 Reset Value: - 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 UNAME1[31:24] 23 22 21 20 19 UNAME1[23:16] 15 14 13 12 11 UNAME1[15:8] 7 6 5 4 3 UNAME1[7:0] • UNAME1: IP Name Part One This field indicates the first part of the ASCII-encoded name of the USBC IP.
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ATSAM4L8/L4/L2 17.7.1.9 IP Name Register 2 Register Name: UNAME2 Access Type: Read-Only Offset: 0x0828 Reset Value: 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 UNAME2[31:24] 23 22 21 20 19 UNAME2[23:16] 15 14 13 12 11 UNAME2[15:8] 7 6 5 4 3 UNAME2[7:0] • UNAME2: IP Name Part Two This field indicates the second part of the ASCII-encoded name of the USBC IP.
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ATSAM4L8/L4/L2 17.7.1.10 Finite State Machine Status Register Register Name: USBFSM Access Type: Read-Only Offset: 0x082C Reset Value: 0x00000009 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - DRDSTATE • DRDSTATE: Dual Role Device State This field indicates the state of the USBC. For Device mode it should always read 9.
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ATSAM4L8/L4/L2 DRDSTATE Description 12 b_wait_discharge: In this state, the B-device waits for the data usb line to discharge (100 us) before becoming Host. 13 b_wait_acon: In this state, the B-device waits for the A-device to signal a connect before becoming B-Host. 14 b_host: In this state, the B-device acts as the Host. 15 b_srp_init: In this state, the B-device attempts to start a session using the SRP protocol.
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ATSAM4L8/L4/L2 17.7.1.11 USB Descriptor Address Register Name: UDESC Access Type: Read-Write Offset: 0x0830 Reset Value: - 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 UDESCA[31:24] 23 22 21 20 19 UDESCA[23:16] 15 14 13 12 11 UDESCA[15:8] 7 6 5 4 3 UDESCA[7:0] • UDESCA: USB Descriptor Address This field contains the address of the USB descriptor. The three least significant bits are always zero.
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ATSAM4L8/L4/L2 17.7.2 USB Device Registers 17.7.2.1 Device General Control Register Register Name: UDCON Access Type: Read/Write Offset: 0x0000 Reset Value: 0x00000100 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - GNAK - 15 14 13 12 11 10 9 8 - - - LS - - RMWKUP DETACH 7 6 5 4 3 2 1 0 ADDEN UADD • GNAK: Global NAK 0: Normal mode.
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ATSAM4L8/L4/L2 17.7.2.2 Device Global Interrupt Register Register Name: UDINT Access Type: Read-Only Offset: 0x0004 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 18 (1) EP7INT EP6INT 17 (1) EP5INT 16 (1) EP4INT(1) - - - 15 14 13 12 11 10 9 8 EP3INT(1) EP2INT(1) EP1INT(1) EP0INT - - - - 7 6 5 4 3 2 1 0 - UPRSM EORSM WAKEUP EORST SOF - SUSP Note: EP8INT 19 (1) 1.
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ATSAM4L8/L4/L2 • SUSP: Suspend Interrupt This bit is cleared when the UDINTCLR.SUSPC bit is written to one to acknowledge the interrupt. This bit is set when a USB “Suspend” idle bus state has been detected for 3 frame periods (J state for 3 ms). This triggers a USB interrupt if SUSPE is one.
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ATSAM4L8/L4/L2 17.7.2.3 Device Global Interrupt Clear Register Register Name: UDINTCLR Access Type: Write-Only Offset: 0x0008 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - UPRSMC EORSMC WAKEUPC EORSTC SOFC - SUSPC Writing a zero to a bit in this register has no effect.
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ATSAM4L8/L4/L2 17.7.2.4 Device Global Interrupt Set Register Register Name: UDINTSET Access Type: Write-Only Offset: 0x000C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - UPRSMS EORSMS WAKEUPS EORSTS SOFS - SUSPS Writing a zero to a bit in this register has no effect.
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ATSAM4L8/L4/L2 17.7.2.5 Device Global Interrupt Enable Register Register Name: UDINTE Access Type: Read-Only Offset: 0x0010 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 (1) EP7INTE 17 (1) EP6INTE 16 (1) EP5INTE EP4INTE(1) - - - 15 14 13 12 11 10 9 8 EP3INTE(1) EP2INTE(1) EP1INTE(1) EP0INTE - - - - 7 6 5 4 3 2 1 0 - UPRSME EORSME WAKEUPE EORSTE SOFE - SUSPE Note: EP8INTE 18 (1) 1.
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ATSAM4L8/L4/L2 17.7.2.
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ATSAM4L8/L4/L2 17.7.2.7 Device Global Interrupt Enable Set Register Register Name: UDINTESET Access Type: Write-Only Offset: 0x0018 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 (1) EP7INTES 17 (1) EP6INTES 16 (1) EP5INTES EP4INTES(1) - - - 15 14 13 12 11 10 9 8 EP3INTES(1) EP2INTES(1) EP1INTES(1) EP0INTES - - - - 7 6 5 4 3 2 1 0 - UPRSMES EORSMES WAKEUPES EORSTES SOFES - SUSPES Note: EP8INTES 18 (1) 1.
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ATSAM4L8/L4/L2 17.7.2.8 Endpoint Enable/Reset Register Register Name: UERST Access Type: Read/Write Offset: 0x001C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - EPEN8(1) 7 6 5 4 3 2 1 0 EPEN7(1) EPEN6(1) EPEN5(1) EPEN4(1) EPEN3(1) EPEN2(1) EPEN1(1) EPEN0 • EPENn: Endpoint n Enable Note: 1. EPENn bits are within the range from EPEN0 to EPEN7.
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ATSAM4L8/L4/L2 17.7.2.9 Device Frame Number Register Register Name: UDFNUM Access Type: Read-Only Offset: 0x0020 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 FNCERR - 7 6 2 1 0 - - - FNUM[10:5] 5 FNUM[4:0] 4 3 • FNCERR: Frame Number CRC Error This bit is cleared upon receiving a USB reset. This bit is set when a corrupted frame number is received.
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ATSAM4L8/L4/L2 17.7.2.10 Endpoint n Configuration Register Register Name: UECFGn, n in [0..7] Access Type: Read/Write Offset: 0x0100 + (n * 0x04) Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 10 9 8 - - - - - EPDIR 7 6 5 3 2 1 0 - EPBK - - - REPNB 11 EPTYPE 4 EPSIZE • REPNB: Redirected endpoint number This field is used to configure the redirected endpoint number.
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ATSAM4L8/L4/L2 • EPSIZE: Endpoint Size This field determines the size of each endpoint bank: EPSIZE Endpoint Size 0 0 0 8 bytes 0 0 1 16 bytes 0 1 0 32 bytes 0 1 1 64 bytes 1 0 0 128 bytes 1 0 1 256 bytes 1 1 0 512 bytes 1 1 1 1024 bytes This field is cleared upon receiving a USB reset (except for the endpoint 0).
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ATSAM4L8/L4/L2 17.7.2.11 Endpoint n Status Register Register Name: UESTAn, n in [0..
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ATSAM4L8/L4/L2 For IN endpoints, this indicates the number of banks filled by the user and ready for IN transfers. When all banks are free an EPnINT interrupt will be triggered if NBUSYBKE is one. For OUT endpoints, this indicates the number of banks filled by OUT transactions from the host. When all banks are busy an EPnINT interrupt will be triggered if NBUSYBKE is one. • RAMACERI: Ram Access Error Interrupt This bit is cleared when the RAMACERIC bit is written to one, acknowledging the interrupt.
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ATSAM4L8/L4/L2 This bit is set, for control endpoints, when the current bank contains a bulk OUT packet (data or status stage). This triggers an EPnINT interrupt if RXOUTE is one. This bit is set for isochronous, bulk and, interrupt OUT endpoints, at the same time as FIFOCON when the current bank is full. This triggers an EPnINT interrupt if RXOUTE is one. This bit is inactive (cleared) for isochronous, bulk and interrupt IN endpoints.
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ATSAM4L8/L4/L2 17.7.2.12 Endpoint n Status Clear Register Register Name: UESTAnCLR, n in [0..
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ATSAM4L8/L4/L2 17.7.2.13 Endpoint n Status Set Register Register Name: UESTAnSET, n in [0..
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ATSAM4L8/L4/L2 17.7.2.14 Endpoint n Control Register Register Name: UECONn, n in [0..
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ATSAM4L8/L4/L2 • KILLBK: Kill IN Bank • • • • • • • • • • • This bit is cleared by hardware after the completion of the “kill packet procedure”. This bit is set when the KILLBKS bit is written to one, killing the last written bank. The user shall wait for this bit to be cleared before trying to process another IN packet. Caution: The bank is cleared when the “kill packet” procedure is completed by the USBC core: If the bank is really killed, the NBUSYBK field is decremented.
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ATSAM4L8/L4/L2 17.7.2.15 Endpoint n Control Clear Register Register Name: UECONnCLR, n in [0..
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ATSAM4L8/L4/L2 17.7.2.16 Endpoint n Control Set Register Register Name: UECONnSET, n in [0..
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ATSAM4L8/L4/L2 17.7.3 USB Host Registers 17.7.3.1 Host General Control Register Register Name: UHCON Access Type: Read/Write Offset: 0x0400 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - RESUME RESET SOFE 7 6 5 4 3 2 1 0 - - - - - - - - • • • RESUME: Send USB Resume Writing a zero to this bit has no effect.
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ATSAM4L8/L4/L2 17.7.3.2 Host Global Interrupt Register Register Name: UHINT Access Type: Read-Only Offset: 0x0404 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - P8INT(1) 15 14 13 12 11 10 9 8 P7INT(1) P6INT(1) P5INT(1) P4INT(1) P3INT(1) P2INT(1) P1INT(1) P0INT 7 6 5 4 3 2 1 0 - HWUPI HSOFI RXRSMI RSMEDI RSTI DDISCI DCONNI Note: 1. PnINT bits are within the range from P0INT to P7INT.
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ATSAM4L8/L4/L2 This bit is set when the device has been removed from the USB bus. • DCONNI: Device Connection Interrupt This bit is cleared when the DCONNIC bit is written to one. This bit is set when a new device has been connected to the USB bus.
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ATSAM4L8/L4/L2 17.7.3.3 Host Global Interrupt Clear Register Register Name: UHINTCLR Access Type: Write-Only Offset: 0x0408 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - HWUPIC HSOFIC RXRSMIC RSMEDIC RSTIC DDISCIC DCONNIC Writing a zero to a bit in this register has no effect.
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ATSAM4L8/L4/L2 17.7.3.4 Host Global Interrupt Set Register Register Name: UHINTSET Access Type: Write-Only Offset: 0x040C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - HWUPIS HSOFIS RXRSMIS RSMEDIS RSTIS DDISCIS DCONNIS - Writing a zero to a bit in this register has no effect.
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ATSAM4L8/L4/L2 17.7.3.5 Host Global Interrupt Enable Register Register Name: UHINTE Access Type: Read-Only Offset: 0x0410 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - P8INTE(1) 15 14 13 12 11 10 9 8 P7INTE(1) P6INTE(1) P5INTE(1) P4INTE(1) P3INTE(1) P2INTE(1) P1INTE(1) P0INTE 7 6 5 4 3 2 1 0 - HWUPIE HSOFIE RXRSMIE RSMEDIE RSTIE DDISCIE DCONNIE Note: 1.
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ATSAM4L8/L4/L2 17.7.3.6 Host Global Interrupt Enable Clear Register Register Name: UHINTECLR Access Type: Write-Only Offset: 0x0414 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - P8INTEC(1) 15 14 13 12 11 10 9 8 P7INTEC(1) P6INTEC(1) P5INTEC(1) P4INTEC(1) P3INTEC(1) P2INTEC(1) P1INTEC(1) P0INTEC 7 6 5 4 3 2 1 0 - HWUPIEC HSOFIEC RXRSMIEC RSMEDIEC RSTIEC DDISCIEC DCONNIEC Note: 1.
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ATSAM4L8/L4/L2 17.7.3.7 Host Global Interrupt Enable Set Register Register Name: UHINTESET Access Type: Write-Only Offset: 0x0418 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - P8INTES(1) 15 14 13 12 11 10 9 8 P7INTES(1) P6INTES(1) P5INTES(1) P4INTES(1) P3INTES(1) P2INTES(1) P1INTES(1) P0INTES 7 6 5 4 3 2 1 0 - HWUPIES HSOFIES RXRSMIES RSMEDIES RSTIES DDISCIES DCONNIES Note: 1.
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ATSAM4L8/L4/L2 17.7.3.8 Pipe Enable/Reset Register Register Name: UPRST Access Type: Read/Write Offset: 0x0041C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - PEN8(1) 7 6 5 4 3 2 1 0 PEN7(1) PEN6(1) PEN5(1) PEN4(1) PEN3(1) PEN2(1) PEN1(1) PEN0 Note: 1. PENn bits are within the range from PEN0 to PEN7.
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ATSAM4L8/L4/L2 17.7.3.
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ATSAM4L8/L4/L2 17.7.3.10 Host Start Of Frame Control Register Register Name: UHSOFC Access Type: Read/Write Offset: 0x0424 Reset Value: 0x00000000yes 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - FLENCE 15 14 13 12 11 10 9 8 - - 2 1 0 FLENC[13:0] FLENC[15:0] 7 6 5 4 3 FLENC[7:0] During a very short period just before transmitting a start of frame, this register is locked.
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ATSAM4L8/L4/L2 17.7.3.11 Pipe n Configuration Register Register Name: UPCFGn, n in [0..7] Access Type: Read/Write Offset: 0x0500 + (n * 0x04) Reset Value: 0x00000000 31 30 29 28 27 26 25 24 BINTERVAL 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - 7 6 3 2 1 0 - PBK - - PTYPE 5 - 4 PSIZE PTOKEN • BINTERVAL: bInterval parameter This field corresponds to the bus access period of the pipe.
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ATSAM4L8/L4/L2 • PSIZE: Pipe Size This field contains the size of each pipe bank. This field is cleared upon sending a USB reset. PSIZE Endpoint Size 0 0 0 8 bytes 0 0 1 16 bytes 0 1 0 32 bytes 0 1 1 64 bytes 1 0 0 128 bytes 1 0 1 256 bytes 1 1 0 512 bytes 1 1 1 1024 bytes • PBK: Pipe Banks This bit selects the number of banks for the pipe. 0: single-bank pipe 1: double bank pipe For control endpoints, a single-bank pipe should be selected.
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ATSAM4L8/L4/L2 17.7.3.12 Pipe n Status Register Register Name: UPSTAn, n in [0..
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ATSAM4L8/L4/L2 • DTSEQ: Data Toggle Sequence This field indicates the data PID of the current bank. For OUT pipes, this field indicates the data toggle of the next packet that will be sent. For IN pipes, this field indicates the data toggle of the received packet stored in the current bank. DTSEQ Data toggle sequence 0 0 Data0 0 1 Data1 1 0 reserved 1 1 reserved • RXSTALLDI: Received STALLed Interrupt This bit is cleared when the RXSTALLDIC bit is written to one.
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ATSAM4L8/L4/L2 17.7.3.13 Pipe n Status Clear Register Register Name: UPSTAnCLR, n in [0..7] Access Type: Write-Only Offset: 0x0560 + (n * 0x04) Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - RAMACERIC - - 7 6 5 4 3 2 1 0 - RXSTALLDIC/ CRCERRIC ERRORFIC NAKEDIC PERRIC TXSTPIC TXOUTIC RXINIC Writing a zero to a bit in this register has no effect.
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ATSAM4L8/L4/L2 17.7.3.14 Pipe n Status Set Register Register Name: UPSTAnSET, n in [0..7] Access Type: Write-Only Offset: 0x0590 + (n * 0x04) Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - RAMACERIS - - 7 6 5 4 3 2 1 0 - RXSTALLDIS/ CRCERRIS ERRORFIC NAKEDIS PERRIS TXSTPIS TXOUTIS RXINIS Writing a zero to a bit in this register has no effect.
PAGE 422
ATSAM4L8/L4/L2 17.7.3.15 Pipe n Control Register Register Name: UPCONn, n in [0..
PAGE 423
ATSAM4L8/L4/L2 This bit is set when the NBUSYBKES bit is written to one.This will enable the Transmitted IN Data interrupt (NBUSYBKE). • RAMACERE: Ram Access Error Interrupt Enable This bit is cleared when the NBUSYBKEC bit is written to one. This will disable the Transmitted IN Data interrupt (NBUSYBKE). This bit is set when the NBUSYBKES bit is written to one.This will enable the Transmitted IN Data interrupt (NBUSYBKE).
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ATSAM4L8/L4/L2 17.7.3.16 Pipe n Control Set Register Register Name: UPCONnSET, n in [0..
PAGE 425
ATSAM4L8/L4/L2 17.7.3.17 Pipe n Control Clear Register Register Name: UPCONnCLR, n in [0..
PAGE 426
ATSAM4L8/L4/L2 17.7.3.18 Pipe n IN Request Register Register Name: UPINRQn, n in [0..7] Access Type: Read/Write Offset: 0x0650 + (n * 0x04) Reset Value: 0x00000001 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - INMODE 7 6 5 4 3 2 1 0 INRQ • INMODE: IN Request Mode Writing a zero to this bit will perform a pre-defined number of IN requests. This number is the INRQ field.
PAGE 427
ATSAM4L8/L4/L2 17.8 Module Configuration The specific configuration for each USBC instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Refer to Section 10. ”Power Manager (PM)” on page 108 for details. Table 17-10. MODULE Clock Name PB Clock Name Description CLK_USBC_APB Clock for the USBC bus interface CLK_USBC_AHB Clock for the USBC AHB interface CGLK The generic clock used for the USBC is GCLK7 Table 17-11.
PAGE 428
ATSAM4L8/L4/L2 18. Advanced Encryption Standard (AESA) Rev: 1.0.2.0 18.1 Features • Compliant with FIPS Publication 197, Advanced Encryption Standard (AES) • 128-bit cryptographic key • Five confidentiality modes of operation as recommended in NIST Special Publication 800-38A, • • • • • 18.
PAGE 429
ATSAM4L8/L4/L2 Finally, AESA supports several hardware countermeasures that are useful for protecting data against differential power analysis attacks (Section 18.4.5 on page 433). Figure 18-1. AESA Block Diagram DMA Controller DMA Controller Hardware Handshaking Interface CLK_HSB CLK_AESA High Speed Bus High Speed Bus Slave IRQ Core Interrupt Controller AESA 18.3 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 18.3.
PAGE 430
ATSAM4L8/L4/L2 The input data for processing is written to an input buffer consisting of four 32-bit registers through the Input Data (IDATA) register address. The input buffer register that is written to when the next write is performed is indicated by the Input Data Word (IDATAW) field in the Data Buffer Pointer (DATABUFPTR) register. This field is incremented by one or wrapped by hardware when a write to the IDATA register address is performed.
PAGE 431
ATSAM4L8/L4/L2 18.4.
PAGE 432
ATSAM4L8/L4/L2 uniquess requirement for counter values across all messages is dependent on the choices of the initial counter values for the messages (see NIST Special Publication 800-38A, Appendix B: Generation of Counter Blocks for recommendations for choosing initial couter values). 18.4.3 DMA Interface AESA is able to interface with a DMA controller, thus allowing the processing of multiple data blocks with minimal CPU intervention.
PAGE 433
ATSAM4L8/L4/L2 Alternatively, the last Nk words of the expanded key can be automatically computed by AESA when a decryption process is initiated if they have not been computed in advance or have become invalid. Note that this will introduce a latency of Nr clock cycles to the first decryption process.
PAGE 434
ATSAM4L8/L4/L2 18.5 User Interface Table 18-2.
PAGE 435
ATSAM4L8/L4/L2 18.5.1 Name: Control Register CTRL Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - SWRST 7 6 5 4 3 2 1 0 - - - - - NEWMSG DKEYGEN ENABLE • SWRST: Software Reset Writing a one to this bit resets the module. Writing a zero to this bit has no effect.
PAGE 436
ATSAM4L8/L4/L2 18.5.
PAGE 437
ATSAM4L8/L4/L2 • CFBS: Cipher Feedback Data Segment Size CFBS Description 0 128 bits 1 64 bits 2 32 bits 3 16 bits 4 8 bits Others Reserved See NIST Special Publications 800-38A, Recommendation for Block Cipher Modes of Operation - Methods and Techniques for information on the CFB mode of operation. See Section 18.4.2 on page 431 for information on operating AESA in the CFB mode.
PAGE 438
ATSAM4L8/L4/L2 18.5.
PAGE 439
ATSAM4L8/L4/L2 18.5.4 Name: Status Register SR Access Type: Read-only Offset: 0x0C Reset Value: 0x00010000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - IBUFRDY 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - ODATARDY • IBUFRDY: Input Buffer Ready This bit is set when the input buffer is ready to receive input data.
PAGE 440
ATSAM4L8/L4/L2 18.5.5 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - IBUFRDY 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - ODATARDY Writing a one to a valid bit in this register sets the corresponding bit in the IMR. Writing a zero to any bit in this register has no effect.
PAGE 441
ATSAM4L8/L4/L2 18.5.6 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x14 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - IBUFRDY 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - ODATARDY Writing a one to a valid bit in this register clears the corresponding bit in the IMR. Writing a zero to any bit in this register has no effect.
PAGE 442
ATSAM4L8/L4/L2 18.5.7 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x18 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - IBUFRDY 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - ODATARDY 1: The corresponding interrupt is enabled. 0: The corresponding interrupt is disabled.
PAGE 443
ATSAM4L8/L4/L2 18.5.8 Name: Key Registers KEYn Access Type: Write-only Offset: 0x20 + (n * 0x04) Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 KEYn[31:24] 23 22 21 20 KEYn[23:16] 15 14 13 12 KEYn[15:8] 7 6 5 4 KEYn[7:0] • KEYn: Key Word n This register stores the nth word of the cryptographic key.
PAGE 444
ATSAM4L8/L4/L2 18.5.
PAGE 445
ATSAM4L8/L4/L2 18.5.10 Name: Input Data Register IDATA Access Type: Write-only Offset: 0x50 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 IDATA[31:24] 23 22 21 20 IDATA[23:16] 15 14 13 12 IDATA[15:8] 7 6 5 4 IDATA[7:0] • IDATA: Input Data A write to this register corresponds to a write to one of the four input buffer registers. The input buffer register that is written to is given by the CTRL.IDATAW field.
PAGE 446
ATSAM4L8/L4/L2 18.5.11 Name: Output Data Register ODATA Access Type: Read-only Offset: 0x60 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ODATA[31:24] 23 22 21 20 ODATA[23:16] 15 14 13 12 ODATA[15:8] 7 6 5 4 ODATA[7:0] • ODATA: Output Data A read from this register corresponds to a read from one of the four output buffer registers. The output buffer register that is read from is given by the CTRL.ODATAW field.
PAGE 447
ATSAM4L8/L4/L2 18.5.12 Name: DRNG Seed Register DRNG Seed Access Type: Write-only Offset: 0x70 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SEED[31:24] 23 22 21 20 SEED[23:16] 15 14 13 12 SEED[15:8] 7 6 5 4 SEED[7:0] • SEED: DRNG Seed A write to this register corresponds to loading a new seed into the DRNG.
PAGE 448
ATSAM4L8/L4/L2 18.5.
PAGE 449
ATSAM4L8/L4/L2 18.5.14 Name: Version Register VERSION Access Type: Read-only Offset: 0xFC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant Number This field is reserved. This field is not associated with any functionality. • VERSION: Version Number This field stores the version number of the module.
PAGE 450
ATSAM4L8/L4/L2 18.6 Module Configuration The specific configuration for each AESA instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Refer to Section 10. ”Power Manager (PM)” on page 108 for details. Table 18-3. Module configuration Feature AESA KeySize 128 bit only Opmode ECB, CBC, CFB, OFB and CTR Countermeasure Implemented Table 18-4.
PAGE 451
ATSAM4L8/L4/L2 19. Asynchronous Timer (AST) Rev: 3.1.1.1 19.1 Features • 32-bit counter with 32-bit prescaler • Clocked Source • • • • • 19.
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ATSAM4L8/L4/L2 19.3 Block Diagram Figure 19-1. Asynchronous Timer Block Diagram CLK_AST CONTROL REGISTER CLK_AST CLK_AST CSSEL WAKE ENABLE REGISTER Wake Control COUNTER VALUE Wake EN PSEL OSC32 RCSYS APB clock 32-bit Prescaler CLK_AST_PRSC CLK_AST_CNT 32-bit Counter OVF GCLK others DIGITAL TUNER REGISTER 19.
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ATSAM4L8/L4/L2 • Peripheral Bus clock (PB clock). This is the clock of the peripheral bus the AST is connected to. • Generic clock (GCLK). One of the generic clocks is connected to the AST. This clock must be enabled before use, and remains enabled in sleep modes when the PB clock is active. • 1kHz clock from the 32kHz oscillator or 32kHz RC Oscillator (CLK_1K). The oscillator must be enabled before use. Selection between OSC32 and RC32 is done inside the Backup Power Manager module.
PAGE 454
ATSAM4L8/L4/L2 • Wait until SR.CLKBUSY reads as zero 19.5.1.2 Changing the Source Clock The CLK_AST_PRSC must be disabled before switching to another source clock. The Clock Busy bit in the Status Register (SR.CLKBUSY) indicates whether the clock is busy or not. This bit is set when the CEN bit in the CLOCK register is changed, and cleared when the CLOCK register can be changed. To change the clock: • Write a zero to CLOCK.CEN to disable the clock, without changing CLOCK.CSSEL • Wait until SR.
PAGE 455
ATSAM4L8/L4/L2 19.5.2.3 Calendar Operation When the CAL bit in the Control Register is one, the counter operates in calendar mode. Before this mode is enabled, the prescaler should be set up to give a pulse every second. The date and time can then be read from or written to the Calendar Value (CALV) register. Time is reported as seconds, minutes, and hours according to the 24-hour clock format. Date is the numeral date of month (starting on 1).
PAGE 456
ATSAM4L8/L4/L2 prescaler when the AST is enabled. The bit is selected by the Interval Select field in the corresponding Periodic Interval Register (PIRn.INSEL), resulting in a periodic interrupt frequency of f CS f PA = -----------------------INSEL + 1 2 where fCS is the frequency of the selected clock source. The corresponding PERn bit in the Status Register (SR) will be set when the selected bit in the prescaler has a 0-to-1 transition.
PAGE 457
ATSAM4L8/L4/L2 (EVE) register, and cleared by writing a one to the corresponding bit in the Event Disable (EVD) register. 19.5.5 AST wakeup The AST can wake up the system by trigerring a PM interrupt. A wakeup can be generated when the counter overflows, when the counter reaches the selected alarm value, or when the selected prescaler bit has a 0-to-1 transition. This wakeup is propagated to the PM and a PM interrupt is generated if enabled.
PAGE 458
ATSAM4L8/L4/L2 If ADD is ‘1’, the prescaler frequency is increased: ⎛ ⎞ ⎜ ⎟ 1 f TUNED = f 0 ⎜ 1 + --------------------------------------------------------------------------------⎟ 256 ⎜ ⎟ roundup ⎛ --------------------⎞ ⋅ ( 2 EXP ) – 1⎠ ⎝ ⎝ VALUE⎠ Note that for these formulas to be within an error of 0.01%, it is recommended that the prescaler bit that is used as the clock for the counter (selected by CR.PSEL) or to trigger the periodic interrupt (selected by PIRn.INSEL) be bit 6 or higher. 19.5.
PAGE 459
ATSAM4L8/L4/L2 19.6 User Interface Table 19-1.
PAGE 460
ATSAM4L8/L4/L2 19.6.1 Name: Control Register CR Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - 15 14 13 12 11 10 9 8 - - - - - - CA1 CA0 7 6 5 4 3 2 1 0 - - - - - CAL PCLR EN PSEL When the SR.BUSY bit is set, writes to this register will be discarded and this register will read as zero.
PAGE 461
ATSAM4L8/L4/L2 19.6.2 Name: Counter Value CV Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 18 17 16 11 10 9 8 3 2 1 0 VALUE[31:24] 23 22 21 20 19 VALUE[23:16] 15 14 13 12 VALUE[15:8] 7 6 5 4 VALUE[7:0] When the SR.BUSY bit is set, writes to this register will be discarded and this register will read as zero. • VALUE: AST Value The current value of the AST counter.
PAGE 462
ATSAM4L8/L4/L2 19.6.3 Name: Status Register SR Access Type: Read-only Offset: 0x08 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - CLKRDY CLKBUSY - - READY BUSY 23 22 21 20 19 18 17 16 - - - - - - - PER0 15 14 13 12 11 10 9 8 - - - - - - - ALARM0 7 6 5 4 3 2 1 0 - - - - - - - OVF • CLKRDY: Clock Ready This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when the SR.
PAGE 463
ATSAM4L8/L4/L2 19.6.4 Name: Status Clear Register SCR Access Type: Write-only Offset: 0x0C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - CLKRDY - - - READY - 23 22 21 20 19 18 17 16 - - - - - - - PER0 15 14 13 12 11 10 9 8 - - - - - - - ALARM0 7 6 5 4 3 2 1 0 - - - - - - - OVF When the SR.BUSY bit is set, writes to this register will be discarded. Writing a zero to a bit in this register has no effect.
PAGE 464
ATSAM4L8/L4/L2 19.6.5 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - CLKRDY - - - READY - 23 22 21 20 19 18 17 16 - - - - - - - PER0 15 14 13 12 11 10 9 8 - - - - - - - ALARM0 7 6 5 4 3 2 1 0 - - - - - - - OVF Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
PAGE 465
ATSAM4L8/L4/L2 19.6.6 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x14 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - CLKRDY - - - READY - 23 22 21 20 19 18 17 16 - - - - - - - PER0 15 14 13 12 11 10 9 8 - - - - - - - ALARM0 7 6 5 4 3 2 1 0 - - - - - - - OVF Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
PAGE 466
ATSAM4L8/L4/L2 19.6.7 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x18 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - CLKRDY - - - READY - 23 22 21 20 19 18 17 16 - - - - - - - PER0 15 14 13 12 11 10 9 8 - - - - - - - ALARM0 7 6 5 4 3 2 1 0 - - - - - - - OVF 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
PAGE 467
ATSAM4L8/L4/L2 19.6.8 Name: Wake Enable Register WER Access Type: Read/Write Offset: 0x1C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - PER0 15 14 13 12 11 10 9 8 - - - - - - - ALARM0 7 6 5 4 3 2 1 0 - - - - - - - OVF When the SR.BUSY bit is set writes to this register will be discarded and this register will read as zero. This register enables the wakeup signal from the AST.
PAGE 468
ATSAM4L8/L4/L2 19.6.9 Name: Alarm Register 0 AR0 Access Type: Read/Write Offset: 0x20 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 18 17 16 11 10 9 8 3 2 1 0 VALUE[31:24] 23 22 21 20 19 VALUE[23:16] 15 14 13 12 VALUE[15:8] 7 6 5 4 VALUE[7:0] When the SR.BUSY bit is set writes to this register will be discarded and this register will read as zero. • VALUE: Alarm Value When the counter reaches this value, an alarm is generated.
PAGE 469
ATSAM4L8/L4/L2 19.6.10 Name: Alarm Register 1 AR1 Access Type: Read/Write Offset: 0x24 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 18 17 16 11 10 9 8 3 2 1 0 VALUE[31:24] 23 22 21 20 19 VALUE[23:16] 15 14 13 12 VALUE[15:8] 7 6 5 4 VALUE[7:0] When the SR.BUSY bit is set writes to this register will be discarded and this register will read as zero. • VALUE: Alarm Value When the counter reaches this value, an alarm is generated.
PAGE 470
ATSAM4L8/L4/L2 19.6.11 Name: Periodic Interval Register 0 PIR0 Access Type: Read/Write Offset: 0x30 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - INSEL When the SR.BUSY bit is set writes to this register will be discarded and this register will read as zero.
PAGE 471
ATSAM4L8/L4/L2 19.6.12 Name: Periodic Interval Register 1 PIR1 Access Type: Read/Write Offset: 0x34 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - INSEL When the SR.BUSY bit is set writes to this register will be discarded and this register will read as zero.
PAGE 472
ATSAM4L8/L4/L2 19.6.13 Name: Clock Control Register CLOCK Access Type: Read/Write Offset: 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - 7 6 5 4 3 2 1 0 - - - - - - - CEN CSSEL When writing to this register, follow the sequence in Section 19.5.1 on page 453.
PAGE 473
ATSAM4L8/L4/L2 19.6.14 Name: Digital Tuner Register DTR Access Type: Read/Write Offset: 0x44 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 VALUE 7 6 5 - - ADD 4 EXP When the SR.BUSY bit is set writes to this register will be discarded and this register will read as zero. • VALUE: 0: The frequency is unchanged.
PAGE 474
ATSAM4L8/L4/L2 19.6.15 Name: Event Enable Register EVE Access Type: Write-only Offset: 0x48 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - PER0 15 14 13 12 11 10 9 8 - - - - - - - ALARM0 7 6 5 4 3 2 1 0 - - - - - - - OVF When the SR.BUSY bit is set writes to this register will be discarded and this register will read as zero. Writing a zero to a bit in this register has no effect.
PAGE 475
ATSAM4L8/L4/L2 19.6.16 Name: Event Disable Register EVD Access Type: Write-only Offset: 0x4C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - PER0 15 14 13 12 11 10 9 8 - - - - - - - ALARM0 7 6 5 4 3 2 1 0 - - - - - - - OVF When the SR.BUSY bit is set writes to this register will be discarded and this register will read as zero. Writing a zero to a bit in this register has no effect.
PAGE 476
ATSAM4L8/L4/L2 19.6.17 Name: Event Mask Register EVM Access Type: Read-only Offset: 0x50 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - PER0 15 14 13 12 11 10 9 8 - - - - - - - ALARM0 7 6 5 4 3 2 1 0 - - - - - - - OVF 0: The corresponding peripheral event is disabled. 1: The corresponding peripheral event is enabled.
PAGE 477
ATSAM4L8/L4/L2 19.6.18 Name: Calendar Value CALV Access Type: Read/Write Offset: 0x54 Reset Value: 0x00000000 31 30 29 28 27 26 25 YEAR 23 22 21 MONTH[3:2] 20 MONTH[1:0] 15 19 18 17 DAY 14 13 12 6 16 HOUR[4] 11 10 HOUR[3:0] 7 24 9 8 1 0 MIN[5:2] 5 4 3 MIN[1:0] 2 SEC When the SR.BUSY bit is set writes to this register will be discarded and this register will read as zero. • YEAR: Year Current year. The year is considered a leap year if YEAR[1:0] = 0.
PAGE 478
ATSAM4L8/L4/L2 19.6.19 Name: Parameter Register PARAMETER Access Type: Read-only Offset: 0xF0 Reset Value: - 31 30 29 - - - 23 22 21 - - - 15 14 13 12 11 10 PIR1WA PIR0WA - NUMPIR - - 7 6 5 4 3 2 - • • • • • • • 28 27 26 25 24 17 16 9 8 PER1VALUE 20 19 18 PER0VALUE DTEXPVALUE NUMAR 1 0 DTEXPWA DT This register gives the configuration used in the specific device. Also refer to the Module Configuration section.
PAGE 479
ATSAM4L8/L4/L2 19.6.20 Name: Version Register VERSION Access Type: Read-only Offset: 0xFC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
PAGE 480
ATSAM4L8/L4/L2 19.7 Module Configuration The specific configuration for each AST instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Refer to Section 10. ”Power Manager (PM)” on page 108 for details. Table 19-3. AST Configuration Feature AST Number of alarm comparators 1 Number of periodic comparators 1 Digital tuner On Table 19-4.
PAGE 481
ATSAM4L8/L4/L2 20. Watchdog Timer (WDT) Rev.: 5.0.1.0 20.1 Features • • • • • 20.2 Watchdog Timer counter with 32-bit counter Timing window watchdog Clocked from system RC oscillator or one of the 32 KHz oscillator (OSC32 or RC32) Configuration lock WDT may be enabled at reset by a fuse Overview The Watchdog Timer (WDT) will reset the device unless it is periodically serviced by the software. This allows the device to recover from a condition that has caused the system to be unstable.
PAGE 482
ATSAM4L8/L4/L2 20.4.1 Power Management When the WDT is enabled, it remains clocked in all sleep modes. It is not possible to enter sleep modes where the source clock of CLK_CNT is stopped. Attempting to do so will result in the chip entering the lowest sleep mode where the source clock is running, leaving the WDT operational. Refer to Section 10. ”Power Manager (PM)” on page 108 for details about sleep modes.
PAGE 483
ATSAM4L8/L4/L2 To change the clock source for CLK_CNT the following steps must be taken. Note that the WDT should always be disabled before changing the CLK_CNT source: 1. Write a zero to the Clock Enable bit in the Control Register (CTRL.CEN), leaving the other bits as they are in the Control Register. This will stop CLK_CNT. 2. Read back CTRL until CTRL.CEN reads zero. The clock has now been stopped. 3. Modify the Clock Source Select bit in CTRL (CTRL.
PAGE 484
ATSAM4L8/L4/L2 Figure 20-2. Basic Mode WDT Timing Diagram, Normal Operation t=t0 T psel Timeout Write one to CLR.WDTCLR Watchdog reset Figure 20-3. Basic Mode WDT Timing Diagram, No Clear within Tpsel t=t0 T psel Timeout Write one to CLR.WDTCLR Watchdog reset 20.5.1.6 Watchdog Reset A watchdog reset will result in a reset and the code will start executing from the boot vector, refer to Section 10. ”Power Manager (PM)” on page 108 for details.
PAGE 485
ATSAM4L8/L4/L2 If the WDT Mode (MODE) bit in the CTRL Register is one, the WDT is in window mode. Note that the CTRL.MODE bit can only be changed when the WDT is disabled (CTRL.EN=0). The PSEL and Time Ban Prescale Select (TBAN) fields in the CTRL Register selects the WDT timeout period Ttimeout = Ttban + Tpsel = (2(TBAN+1) + 2(PSEL+1)) / fclk_cnt where Ttban sets the time period when clearing the WDT counter by writing to the CLR.WDTCLR bit is not allowed.
PAGE 486
ATSAM4L8/L4/L2 Figure 20-5. Window Mode WDT Timing Diagram, clearing within Ttban, resulting in watchdog reset. t=t0 T tban T psel Timeout Write one to CLR.WDTCLR Watchdog reset 20.5.3 Interrupt Mode In interrupt mode, the WDT can generate an interrupt request when the WDT counter times out. Interrupt mode is enabled by writing a one to the Interrupt Mode bit in the CTRL register (CTRL.IM). When interrupt mode is enabled, the Watchdog Interrupt bit in the Interrupt Status Register (ISR.
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ATSAM4L8/L4/L2 Figure 20-6. Interrupt Mode WDT Timing Diagram T im e o u t t= t 0 T psel T psel T im e o u t IS R .W IN T IM R .W IN T W a tc h d o g in te rru p t W a tc h d o g re s e t C le a r in te rru p t Figure 20-7. Interrupt Mode WDT Timing Diagram, not clearing the interrupt.
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ATSAM4L8/L4/L2 20.5.4 Disabling the WDT The WDT is disabled by writing a zero to the CTRL.EN bit. When disabling the WDT no other bits in the CTRL Register should be changed until the CTRL.EN bit reads back as zero. If the CTRL.CEN bit is written to zero, the CTRL.EN bit will never read back as zero if changing the value from one to zero. 20.5.5 Flash Calibration The WDT can be enabled at reset. This is controlled by the WDTAUTO fuse.
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ATSAM4L8/L4/L2 20.6 User Interface Table 20-1.
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ATSAM4L8/L4/L2 20.6.1 Name: Control Register CTRL Access Type: Read/Write Offset: 0x000 Reset Value: 0x00010080 31 30 29 28 27 26 25 24 19 18 17 16 CSSEL CEN 9 8 KEY 23 22 21 - 20 TBAN 15 14 13 12 11 10 - - - 7 6 5 4 3 2 1 0 FCD - - IM SFV MODE DAR EN PSEL • KEY • • • • • • • This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to be effective. This field always reads as zero.
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ATSAM4L8/L4/L2 • MODE: WDT Mode 0: The WDT is in basic mode, only PSEL time is used. 1: The WDT is in window mode. Total timeout period is now TBAN+PSEL. Writing to this bit when the WDT is enabled has no effect. • DAR: WDT Disable After Reset 0: After a watchdog reset, the WDT will still be enabled. 1: After a watchdog reset, the WDT will be disabled. • EN: WDT Enable 0: WDT is disabled. 1: WDT is enabled. After writing to this bit the read back value will not change until the WDT is enabled/disabled.
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ATSAM4L8/L4/L2 20.6.2 Name: Clear Register CLR Access Type: Write-only Offset: 0x004 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - WDTCLR When the Watchdog Timer is enabled, this Register must be periodically written within the window time frame or within the watchdog timeout period, to prevent a watchdog reset.
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ATSAM4L8/L4/L2 20.6.3 Name: Status Register SR Access Type: Read-only Offset: 0x008 Reset Value: 0x00000003 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - CLEARED WINDOW • CLEARED: WDT Counter Cleared This bit is cleared when writing a one to the CLR.WDTCLR bit. This bit is set when clearing the WDT counter is done.
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ATSAM4L8/L4/L2 20.6.4 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x00C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - WINT - - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
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ATSAM4L8/L4/L2 20.6.5 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x010 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - WINT - - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
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ATSAM4L8/L4/L2 20.6.6 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x014 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - WINT - - 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
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ATSAM4L8/L4/L2 20.6.7 Name: Interrupt Status Register ISR Access Type: Read-only Offset: 0x018 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - WINT - - 0: The corresponding interrupt is cleared. 1: The corresponding interrupt is pending. This bit is cleared when the corresponding bit in ICR is written to one.
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ATSAM4L8/L4/L2 20.6.8 Name: Interrupt Clear Register ICR Access Type: Write-only Offset: 0x01C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - WINT - - Writing a zero to a bit in this register has no effect.
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ATSAM4L8/L4/L2 20.6.9 Name: Version Register VERSION Access Type: Read-only Offset: 0x3FC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
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ATSAM4L8/L4/L2 20.7 Module Configuration The specific configuration for each WDT instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Refer to Section 10. ”Power Manager (PM)” on page 108 for details. Table 20-2. WDT Clocks Clock Name Description CLK_WDT Clock for the WDT bus interface Table 20-3.
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ATSAM4L8/L4/L2 21. External Interrupt Controller (EIC) Rev: 3.0.2.0 21.1 Features • • • • • • • 21.2 Dedicated interrupt request for each interrupt Individually maskable interrupts Interrupt on rising or falling edge Interrupt on high or low level Asynchronous interrupts for sleep modes without clock Filtering of interrupt lines Non-Maskable NMI interrupt Overview The External Interrupt Controller (EIC) allows pins to be configured as external interrupts.
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ATSAM4L8/L4/L2 21.4 I/O Lines Description Table 21-1. 21.5 I/O Lines Description Pin Name Pin Description Type NMI Non-Maskable Interrupt Input EXTINTn External Interrupt Input Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 21.5.1 I/O Lines The external interrupt pins (EXTINTn and NMI) may be multiplexed with I/O Controller lines.
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ATSAM4L8/L4/L2 Each external interrupt INTn can be configured to produce an interrupt on rising or falling edge, or high or low level. External interrupts are configured by the MODE, EDGE, and LEVEL registers. Each interrupt has a bit INTn in each of these registers. Writing a zero to the INTn bit in the MODE register enables edge triggered interrupts, while writing a one to the bit enables level triggered interrupts.
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ATSAM4L8/L4/L2 Figure 21-2. Timing Diagram, Synchronous Interrupts, High Level or Rising Edge CLK_SYNC EXTINTn/NMI ISR.INTn: FILTER off ISR.INTn: FILTER on Figure 21-3. Timing Diagram, Synchronous Interrupts, Low Level or Falling Edge CLK_SYNC EXTINTn/NMI ISR.INTn: FILTER off ISR.INTn: FILTER on 21.6.3 Non-Maskable Interrupt The NMI supports the same features as the external interrupts, and is accessed through the same registers. The description in Section 21.6.
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ATSAM4L8/L4/L2 When CLK_SYNC is stopped only asynchronous interrupts remain active, and any short spike on this interrupt will wake up the device. EIC_WAKE will restart CLK_SYNC and ISR will be updated on the first rising edge of CLK_SYNC. Figure 21-4. Timing Diagram, Asynchronous Interrupts CLK_SYNC CLK_SYNC E X T IN T n /N M I 21.6.5 E X T IN T n /N M I IS R .IN T n : ris in g E D G E o r h ig h LEVEL IS R .
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ATSAM4L8/L4/L2 21.7 User Interface Table 21-2.
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ATSAM4L8/L4/L2 21.7.
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ATSAM4L8/L4/L2 21.7.
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ATSAM4L8/L4/L2 21.7.
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ATSAM4L8/L4/L2 21.7.
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ATSAM4L8/L4/L2 21.7.
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ATSAM4L8/L4/L2 21.7.
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ATSAM4L8/L4/L2 21.7.
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ATSAM4L8/L4/L2 21.7.
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ATSAM4L8/L4/L2 21.7.
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ATSAM4L8/L4/L2 21.7.
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ATSAM4L8/L4/L2 21.7.
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ATSAM4L8/L4/L2 21.7.
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ATSAM4L8/L4/L2 21.7.
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ATSAM4L8/L4/L2 21.7.
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ATSAM4L8/L4/L2 21.7.15 Name: Version Register VERSION Access Type: Read-only Offset: 0x3FC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - 7 6 5 4 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VERSION: Version number Version number of the module. No functionality associated.
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ATSAM4L8/L4/L2 21.8 Module Configuration The specific configuration for each EIC instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Refer to Section 10. ”Power Manager (PM)” on page 108 for details. Table 21-3. EIC Configuration Feature EIC Number of external interrupts, including NMI 9 Table 21-4. EIC Clocks Clock Name Description CLK_EIC Clock for the EIC bus interface Table 21-5.
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ATSAM4L8/L4/L2 22. Frequency Meter (FREQM) Rev: 3.1.1.1 22.1 Features • • • • 22.2 Accurately measures a clock frequency Selectable reference clock A selectable clock can be measured Ratio can be measured with 24-bit accuracy Overview The Frequency Meter (FREQM) can be used to accurately measure the frequency of a clock by comparing it to a known reference clock. 22.3 Block Diagram Figure 22-1. Frequency Meter Block Diagram CLKSEL START CLK_MSR Counter VALUE CLK_REF Timer Trigger REFSEL 22.
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ATSAM4L8/L4/L2 FREQM interrupts can wake up the device from sleep modes when the measurement is done, but only from sleep modes where CLK_FREQM is running. Refer to Section 10. ”Power Manager (PM)” on page 108 for details. 22.4.2 Clocks The clock for the FREQM bus interface (CLK_FREQM) is generated by the Power Manager. It is recommended to disable the FREQM before disabling the clock, to avoid freezing the FREQM ia an undefined state.
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ATSAM4L8/L4/L2 • Wait until the SR.RCLKBUSY bit reads as zero. To disable CLK_REF: • Write a zero to the MODE.REFCEN to disable he clock, without changing the other bits/fields in the Mode register. • Wait until the SR.RCLKBUSY bit reads as zero. 22.5.1.1 22.5.2 Cautionary Note Note that if clock selected as source for CLK_REF is stopped during a measurement, this will not be detected by the FREQM. The BUSY bit in the STATUS register will never be cleared, and the DONE interrupt will never be triggered.
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ATSAM4L8/L4/L2 22.6 User Interface Table 22-1.
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ATSAM4L8/L4/L2 22.6.1 Name: Control Register CTRL Access Type: Write-only Offset: 0x000 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - START • START Writing a zero to this bit has no effect. Writing a one to this bit will start a measurement.
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ATSAM4L8/L4/L2 22.6.2 Name: Mode Register MODE Access Type: Read/Write Offset: 0x004 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 REFCEN - - - - - - - 23 22 21 20 19 18 17 16 - - - 15 14 13 CLKSEL 12 11 10 9 8 2 1 0 REFNUM 7 6 5 4 3 - - - - - REFSEL • REFCEN: Reference Clock Enable 0: The reference clock is disabled 1: The reference clock is enabled • CLKSEL: Clock Source Selection Selects the source for CLK_MSR.
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ATSAM4L8/L4/L2 22.6.3 Status Register Name: STATUS Access Type: Read-only Offset: 0x008 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - RCLKBUSY BUSY • RCLKBUSY: FREQM Reference Clock Status 0: The FREQM ref clk is ready, so a measurement can start.
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ATSAM4L8/L4/L2 22.6.4 Value Register Name: VALUE Access Type: Read-only Offset: 0x00C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 VALUE[23:16] 15 14 13 12 VALUE[15:8] 7 6 5 4 VALUE[7:0] • VALUE: Result from measurement.
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ATSAM4L8/L4/L2 22.6.5 Interrupt Enable Register Name: IER Access Type: Write-only Offset: 0x010 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - RCLKRDY DONE Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
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ATSAM4L8/L4/L2 22.6.6 Interrupt Disable Register Name: IDR Access Type: Write-only Offset: 0x014 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - RCLKRDY DONE Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
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ATSAM4L8/L4/L2 22.6.7 Interrupt Mask Register Name: IMR Access Type: Read-only Offset: 0x018 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - RCLKRDY DONE 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
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ATSAM4L8/L4/L2 22.6.8 Interrupt Status Register Name: ISR Access Type: Read-only Offset: 0x01C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - RCLKRDY DONE 0: The corresponding interrupt is cleared. 1: The corresponding interrupt is pending.
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ATSAM4L8/L4/L2 22.6.9 Interrupt Clear Register Name: ICR Access Type: Write-only Offset: 0x020 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - RCLKRDY DONE Writing a zero to a bit in this register has no effect.
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ATSAM4L8/L4/L2 22.6.10 Name: Version Register VERSION Access Type: Read-only Offset: 0x3FC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
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ATSAM4L8/L4/L2 22.7 Module Configuration The specific configuration for each FREQM instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Refer to Section 10. ”Power Manager (PM)” on page 108 for details. Table 22-2. FREQM Clock Name Clock Name Description CLK_FREQM Clock for the FREQM bus interface CLK_MSR Measured clock CLK_REF Reference clock Table 22-3.
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ATSAM4L8/L4/L2 Table 22-5.
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ATSAM4L8/L4/L2 23. General-Purpose Input/Output Controller (GPIO) Rev: 2.1.5.5 23.1 Features • • • • • • • • • • • 23.
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ATSAM4L8/L4/L2 23.4 I/O Lines Description Pin Name Description Type GPIOn GPIO pin n Digital 23.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 23.5.1 Power Management If the CPU enters a sleep mode that disables clocks used by the GPIO, the GPIO will stop functioning and resume operation after the system wakes up from sleep mode.
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ATSAM4L8/L4/L2 23.6 Functional Description The GPIO controls the I/O pins of the microcontroller. The control logic associated with each pin is shown in the figure below. Figure 23-2. Overview of the GPIO PDER* PUER* ODER 1 0 Periph. Func. A Output Pullup, Pulldown and buskeeper 0 Periph.Func. B Periph. Func. C 1 ....
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ATSAM4L8/L4/L2 23.6.1 Basic Operation 23.6.1.1 Module Configuration The GPIO user interface registers are organized into ports and each port controls 32 different GPIO pins. Most of the registers supports bit wise access operations such as set, clear and toggle in addition to the standard word access. For details regarding interface registers, refer to Section 23.7. 23.6.1.2 Available Features The GPIO features implemented are device dependent, and not all functions are implemented on all pins.
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ATSAM4L8/L4/L2 23.6.2 23.6.2.1 Advanced Operation Peripheral I/O Pin Control When a GPIO pin is assigned to a peripheral function, i.e. the corresponding bit in GPER is zero, output and output enable is controlled by the selected peripheral pin. In addition the peripheral may control some or all of the other GPIO pin functions listed in Table 23-1, if the peripheral supports those features. All pin features not controlled by the selected peripheral is controlled by the GPIO.
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ATSAM4L8/L4/L2 Figure 23-3. Output Pin Timings CLK_GPIO Write OVR to 1 Write OVR to 0 PB Access PB Access OVR / I/O Line PVR 23.6.2.4 Pin Output Driver Control The GPIO has registers for controlling output drive properties of each pin, such as output driving capability and slew rate control. The driving capability is controlled by the Output Driving Capability Registers (ODCRn) and the slew rate settings are controlled by the Output Slew Rate Registers (OSRRn).
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ATSAM4L8/L4/L2 tion of 2 CLK_GPIO cycles or more is accepted. For pulse durations between 1 and 2 CLK_GPIO cycles, the pulse may or may not be taken into account, depending on the precise timing of its occurrence. Thus for a pulse to be guaranteed visible it must exceed 2 CLK_GPIO cycles, whereas for a glitch to be reliably filtered out, its duration must not exceed 1 CLK_GPIO cycle. The filter introduces 2 clock cycles latency. The glitch filters are controlled by the Glitch Filter Enable Register (GFER).
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ATSAM4L8/L4/L2 events are enabled. Peripheral Events are also affected by the Input Glitch Filter settings. See Section 23.6.2.7 for more information. A peripheral event can be generated on each GPIO pin. Each port can then have up to 32 peripheral event generators. Groups of eight peripheral event generators in each port are ORed together to form a peripheral event line, so that each port has four peripheral event lines connected to the Peripheral Event System.
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ATSAM4L8/L4/L2 23.7 User Interface The GPIO controller manages all the GPIO pins. The pins are managed as 32-bit ports that are configurable through a Peripheral Bus (PB) interface. Each port has a set of configuration registers. The overall memory map of the GPIO is shown below. The number of pins and hence the number of ports is product specific. Figure 23-6. Port Configuration Registers 0x0000 Port 0 Configuration Registers 0x0200 Port 1 Configuration Registers 0x0400 ….
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ATSAM4L8/L4/L2 ten to one. Again all bits written to zero remain unchanged. Note that for some registers (e.g. IFR), not all access methods are permitted. Note that for ports with less than 32 bits, the corresponding control registers will have unused bits. This is also the case for features that are not implemented for a specific pin. Writing to an unused bit will have no effect. Reading unused bits will always return 0. Table 23-2.
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ATSAM4L8/L4/L2 Table 23-2. GPIO Register Memory Map Config.
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ATSAM4L8/L4/L2 Table 23-2. GPIO Register Memory Map Offset Register Function Register Name Access Reset Config.
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ATSAM4L8/L4/L2 23.7.2 Name: GPIO Enable Register GPER Access: Read/Write, Set, Clear, Toggle Offset: 0x000, 0x004, 0x008, 0x00C Reset Value: - 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: GPIO Enable 0: A peripheral function controls the corresponding pin.
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ATSAM4L8/L4/L2 23.7.
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ATSAM4L8/L4/L2 23.7.
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ATSAM4L8/L4/L2 23.7.
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ATSAM4L8/L4/L2 23.7.
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ATSAM4L8/L4/L2 23.7.7 Name: Output Value Register OVR Access: Read/Write, Set, Clear, Toggle Offset: 0x050, 0x054, 0x058, 0x05C Reset Value: - 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Output Value 0: The value to be driven on the GPIO pin is 0.
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ATSAM4L8/L4/L2 23.7.8 Name: Pin Value Register PVR Access: Read-only Offset: 0x060, 0x064, 0x068, 0x06C Reset Value: Depending on pin states 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Pin Value 0: The GPIO pin is at level zero. 1: The GPIO pin is at level one.
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ATSAM4L8/L4/L2 23.7.
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ATSAM4L8/L4/L2 23.7.
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ATSAM4L8/L4/L2 23.7.11 Name: Interrupt Enable Register IER Access: Read/Write, Set, Clear, Toggle Offset: 0x090, 0x094, 0x098, 0x09C Reset Value: - 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Interrupt Enable 0: Interrupt is disabled for the corresponding pin.
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ATSAM4L8/L4/L2 23.7.
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ATSAM4L8/L4/L2 23.7.
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ATSAM4L8/L4/L2 23.7.
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ATSAM4L8/L4/L2 23.7.15 Name: Interrupt Flag Register IFR Access: Read, Clear Offset: 0x0D0, 0x0D8 Reset Value: - 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Interrupt Flag 0: No interrupt condition has been detected on the corresponding pin.
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ATSAM4L8/L4/L2 23.7.
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ATSAM4L8/L4/L2 23.7.
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ATSAM4L8/L4/L2 23.7.
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ATSAM4L8/L4/L2 23.7.
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ATSAM4L8/L4/L2 23.7.20 Name: Event Enable Register EVER Access: Read/Write, Set, Clear, Toggle Offset: 0x180, 0x184, 0x188, 0x18C Reset Value: - 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Event Enable 0: Peripheral Event is disabled for the corresponding pin.
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ATSAM4L8/L4/L2 23.7.21 Name: Parameter Register PARAMETER Access Type: Read-only Offset: 0x1F8 Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 PARAMETER 23 22 21 20 PARAMETER 15 14 13 12 PARAMETER 7 6 5 4 PARAMETER • PARAMETER: 0: The corresponding pin is not implemented in this GPIO port. 1: The corresponding pin is implemented in this GPIO port. There is one PARAMETER register per GPIO port.
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ATSAM4L8/L4/L2 23.7.22 Name: Version Register VERSION Access Type: Read-only Offset: 0x1FC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 1 0 VARIANT 11 10 VERSION[11:8] 3 2 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
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ATSAM4L8/L4/L2 23.8 Module Configuration The specific configuration for each GPIO instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Refer to Section 10. ”Power Manager (PM)” on page 108 for details. Table 23-3. GPIO Configuration Feature 48 pin package 64-pin package 100-pin package Number of GPIO ports 1 2 3 Number of peripheral functions 8 8 8 Table 23-4.
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ATSAM4L8/L4/L2 Table 23-6.
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ATSAM4L8/L4/L2 24. Universal Synchronous Asynchronous Receiver Transmitter (USART) Rev: 6.0.2.6 24.1 Features • Configurable baud rate generator • 5- to 9-bit full-duplex, synchronous and asynchronous, serial communication • • • • • • • 24.2 – 1, 1.
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ATSAM4L8/L4/L2 frame lengths with the time-out feature. The USART supports several operating modes, providing an interface to RS485, LIN, and SPI buses, with ISO7816 T=0 and T=1 smart card slots, and infrared transceivers, and modem port connections. Communication with slow and remote devices is eased by the timeguard. Duplex multidrop communication is supported by address and data differentiation through the parity bit.
PAGE 576
ATSAM4L8/L4/L2 Figure 24-2. USART Block Diagram Peripheral DMA Controller Channel Channel I/O Controller USART RXD Receiver RTS Interrupt Controller USART Interrupt TXD Transmitter CTS CLK_USART Power Manager DIV BaudRate Generator CLK CLK_USART/DIV User Interface Peripheral bus Table 24-1.
PAGE 577
ATSAM4L8/L4/L2 24.4 I/O Lines Description Table 24-2.
PAGE 578
ATSAM4L8/L4/L2 24.6 24.6.1 Functional Description USART Operating Modes The USART can operate in several modes: • Normal • RS485, described in Section 24.6.5 ”RS485 Mode” on page 588 • Hardware handshaking, described in Section 24.6.6 ”Hardware Handshaking” on page 589 • Modem, described in Section 24.6.7 ”Modem Mode” on page 590 • ISO7816, described in Section 24.6.8 ”ISO7816 Mode” on page 591 • IrDA, described in Section 24.6.9 ”IrDA Mode” on page 594 • LIN Master, described in Section 24.6.
PAGE 579
ATSAM4L8/L4/L2 4. Check that CSR.TXRDY and/or CSR.RXRDY is one before writing to THR and/or reading from RHR respectively 24.6.2.1 Receiver and Transmitter Control After a reset, the transceiver is disabled. The receiver/transmitter is enabled by writing a one to the Receiver Enable/Transmitter Enable bit in the Control Register (CR.RXEN/CR.TXEN) respectively. They may be enabled together and can be configured both before and after they have been enabled.
PAGE 580
ATSAM4L8/L4/L2 Figure 24-4. Transmitter Status Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write THR TXRDY TXEMPTY 24.6.2.3 Asynchronous Receiver If the USART is configured in an asynchronous operating mode (MR.SYNC is zero), the receiver will oversample the RXD input line by either 8 or 16 times the Baud Rate Clock, as selected by the Oversampling Mode bit (MR.OVER).
PAGE 581
ATSAM4L8/L4/L2 Figure 24-6. Asynchronous Mode Character Reception Example: 8-bit, Parity Enabled Baud Rate Clock RXD Start Detection 16 16 16 16 16 16 16 16 16 16 samples samples samples samples samples samples samples samples samples samples D0 24.6.2.4 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit Synchronous Receiver In synchronous mode (MR.SYNC is one), the receiver samples the RXD signal on each rising edge of the Baud Rate Clock, as illustrated in Figure 24-7.
PAGE 582
ATSAM4L8/L4/L2 Interrupt Mask Register (IMR.RXRDY) is set. If CSR.RXRDY is already set, RHR will be overwritten and the Overrun Error bit (CSR.OVRE) is set. An interrupt request is generated if the Overrun Error bit in IMR is set. Reading RHR will clear CSR.RXRDY, and writing a one to the Reset Status bit in the Control Register (CR.RSTSTA) will clear CSR.OVRE. Refer to Figure 248. 24.6.3 24.6.3.1 Other Considerations Parity The USART supports five parity modes, selected by MR.
PAGE 583
ATSAM4L8/L4/L2 24.6.3.2 Multidrop Mode If MR.PAR is either 0x6 or 0x7, the USART runs in Multidrop mode. This mode differentiates data and address characters. Data has the parity bit zero and addresses have a one. By writing a one to the Send Address bit (CR.SENDA) the user will cause the next character written to THR to be transmitted as an address. Receiving a character with a one as parity bit will report parity error by setting CSR.PARE.
PAGE 584
ATSAM4L8/L4/L2 24.6.3.4 Receiver Time-out The Time-out Value field in the Receiver Time-out Register (RTOR.TO) enables handling of variable-length frames by detection of selectable idle durations on the RXD line. The value written to TO is loaded to a decremental counter, and unless it is zero, a time-out will occur when the amount of inactive bit periods matches the initial counter value. If a time-out has not occurred, the counter will reload and restart every time a new character arrives.
PAGE 585
ATSAM4L8/L4/L2 24.6.3.5 Framing Error The receiver is capable of detecting framing errors. A framing error has occurred if a stop bit reads as zero. This can occur if the transmitter and receiver are not synchronized. A framing error is reported by CSR.FRAME as soon as the error is detected, at the middle of the stop bit. An interrupt request is generated if the Framing Error bit in the Interrupt Mask Register (IMR.FRAME) is set. CSR.FRAME is cleared by writing a one to CR.RSTSTA. Figure 24-12.
PAGE 586
ATSAM4L8/L4/L2 24.6.3.7 24.6.4 Receive Break A break condition is assumed when incoming data, parity, and stop bits are zero. This corresponds to a framing error, but CSR.FRAME will remain zero while the Break Received/End of Break bit (CSR.RXBRK) is set. An interrupt request is generated if the Breadk Received/End of Break bit in the Interrupt Mask Register is set (IMR.RXBRK). Writing a one to CR.RSTSTA will clear CSR.RXBRK. An end of break will also set CSR.
PAGE 587
ATSAM4L8/L4/L2 This gives a maximum baud rate of CLK_USART divided by 8, assuming that CLK_USART is the fastest clock available, and that MR.OVER is one. 24.6.4.2 Table 24-7. Baud Rate Calculation Example Table 24-7 shows calculations based on the CD field to obtain 38400 baud from different source clock frequencies. This table also shows the actual resulting baud rate and error.
PAGE 588
ATSAM4L8/L4/L2 the Fractional Part field in BRGR (BRGR.FP), and is activated by giving it a non-zero value. The resolution is one eighth of CD. The resulting baud rate is calculated using the following formula: SelectedClock BaudRate = ------------------------------------------------------------------⎛ 8 ( 2 – OVER ) ⎛ CD + FP -------⎞ ⎞ ⎝ ⎝ 8 ⎠⎠ The modified architecture is shown in Figure 24-15. Figure 24-15.
PAGE 589
ATSAM4L8/L4/L2 Figure 24-16. Typical Connection to a RS485 Bus USART RXD Differential Bus TXD RTS If a timeguard has been configured the RTS pin will remain high for the duration specified in TG, as shown in Figure 24-17. Figure 24-17. Example of RTS Drive with Timeguard Enabled TG = 4 Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write THR TXRDY TXEMPTY RTS 24.6.
PAGE 590
ATSAM4L8/L4/L2 Writing 0x2 to the MR.MODE field configures the USART to operate in hardware handshaking mode. The receiver will drive its RTS pin high when disabled or when the Reception Buffer Full bit (CSR.RXBUFF) is set by the Buffer Full signal from the Peripheral DMA controller. If the receiver RTS pin is high, the transmitter CTS pin will also be high and only the active character transmissions will be completed.
PAGE 591
ATSAM4L8/L4/L2 Table 24-8. Circuit References USART Pin V.24 CCITT Direction DSR 6 107 From terminal to modem DCD 8 109 From terminal to modem RI 22 125 From terminal to modem The DTR pin is controlled by the DTR enable and disable bits in CR (CR.DTREN and CR.DTRDIS). Writing a one to CR.DTRDIS drives DTR high, and writing a one to CR.DTREN drives DTR low. The RTS pin is controlled automatically. Detected level changes are reported by the respective Input Change bits in CSR (CSR.RIIC, CSR.
PAGE 592
ATSAM4L8/L4/L2 • B is the bit rate • Di is the bit-rate adjustment factor • Fi is the clock frequency division factor • f is the ISO7816 clock frequency (Hz) Di is a binary value encoded on a 4-bit field, named DI, as represented in Table 24-9. Table 24-9. Binary and Decimal Values for Di DI field 0001 0010 0011 0100 0101 0110 1000 1001 1 2 4 8 16 32 12 20 Di (decimal) Fi is a binary value encoded on a 4-bit field, named FI, as represented in Table 24-10. Table 24-10.
PAGE 593
ATSAM4L8/L4/L2 Figure 24-22. Elementary Time Unit (ETU) FI_DI_RATIO ISO7816 Clock Cycles ISO7816 Clock on CLK ISO7816 I/O Line on TXD 1 ETU 24.6.8.3 Protocol T=0 In T=0 protocol, a character is made up of one start bit, eight data bits, one parity bit, and a two bit period guard time. During the guard time, the line will be high if the receiver does not signal a parity error, as shown in Figure 24-23.
PAGE 594
ATSAM4L8/L4/L2 24.6.8.7 Transmit Character Repetition The USART can be configured to automatically re-send a character if it receives a NACK. Writing a non-zero value to MR.MAX_ITERATION will enable and determine the number of consecutive re-transmissions. If the number of unsuccessful re-transmissions equals MAX_ITERATION, the iteration bit (CSR.ITER) is set. An interrupt request is generated if the ITER bit in the Interrupt Mask Register (IMR.ITER) is set. Writing a one to the Reset Iteration bit (CR.
PAGE 595
ATSAM4L8/L4/L2 24.6.9.1 IrDA Modulation The RZI modulation scheme is used, where a zero is represented by a light pulse 3/16 of a bit period, and no pulse to represent a one. Some examples of signal pulse duration are shown in Table 24-12. Table 24-12. IrDA Pulse Duration Baud Rate Pulse Duration (3/16) 2.4 Kbit/s 78.13 µs 9.6 Kbit/s 19.53 µs 19.2 Kbit/s 9.77 µs 38.4 Kbit/s 4.88 µs 57.6 Kbit/s 3.26 µs 115.2 Kbit/s 1.63 µs Figure 24-26 shows an example of character transmission.
PAGE 596
ATSAM4L8/L4/L2 Table 24-13. IrDA Baud Rate Error (Continued) Peripheral Clock 24.6.9.3 Baud Rate CD Baud Rate Error Pulse Time 3 686 400 38 400 6 0.00% 4.88 20 000 000 38 400 33 1.38% 4.88 32 768 000 38 400 53 0.63% 4.88 40 000 000 38 400 65 0.16% 4.88 3 686 400 19 200 12 0.00% 9.77 20 000 000 19 200 65 0.16% 9.77 32 768 000 19 200 107 0.31% 9.77 40 000 000 19 200 130 0.16% 9.77 3 686 400 9 600 24 0.00% 19.53 20 000 000 9 600 130 0.16% 19.
PAGE 597
ATSAM4L8/L4/L2 24.6.10.1 Modes of Operation Changing LIN mode after initial configuration must be followed by a transceiver software reset in order to avoid unpredictable behavior. 24.6.10.2 Receiver and Transmitter Control See Section “24.6.2.1” on page 579. 24.6.10.3 Baud Rate Configuration The LIN nodes baud rate is configured in the Baud Rate Generator Register (BRGR), See Section “24.6.4.1” on page 586.
PAGE 598
ATSAM4L8/L4/L2 is not received within the time defined in THeader_Maximum, the Lin Header Time-out error (CSR.LINHTE) is generated (see Section 24.6.10.13). An interrupt request is generated if IMR.LINHTE is set. Writing a one to CR.RSTSTA will clear CSR.LINHTE, CSR.LINBK, and CSR.LINID. Figure 24-29.
PAGE 599
ATSAM4L8/L4/L2 Figure 24-31.
PAGE 600
ATSAM4L8/L4/L2 – 4 ≤ α ≤ +4 -1 < β < +1 Minimum nominal clock frequency without a fractional part: ⎛ ⎞ ⎜ [---------------------------------------------------------------------------------------------4 × 8 × ( 2 – OVER ) + 1 ] × Baudrate-⎟ F Nom ( min ) = ⎜ 100 × ⎟ Hz – 15- + 1⎞ × 1% ⎜ ⎟ ⎛ --------8 × ⎝ ⎠ ⎝ 100 ⎠ Examples: • Baud rate = 20 kbit/s, OVER=0 (Oversampling 16x) => FNom(min) = 19.12MHz • Baud rate = 20 kbit/s, OVER=1 (Oversampling 8x) => FNom(min) = 9.
PAGE 601
ATSAM4L8/L4/L2 24.6.10.10 LIN Response Data Length The response data length is the number of data fields (bytes), excluding the checksum. Figure 24-32. Response Data Length User configuration: 1 - 256 data fields (DLC+1) Identifier configuration: 2/4/8 data fields Sync Break Sync Field Identifier Field Data Field Data Field Data Field Data Field Checksum Field The response data length can be configured, either by the user, or automatically by bits 4 and 5 in the Identifier (LINIR.
PAGE 602
ATSAM4L8/L4/L2 Figure 24-33. Frame Slot Mode with Automatic Checksum Frame slot = TFrame_Maximum Frame Header Break Synch Data3 Interframe space Response space Protected Identifier Response Data 1 Data N-1 Data N Checksum TXRDY Frame Slot Mode Frame Slot Mode Disabled Enabled Write LINID Write THR Data 1 Data 2 Data 3 Data N LINTC The minimum frame slot size is determined by TFrame_Maximum, and calculated below (all values in bit periods): • THeader_Nominal = 34 • TFrame_Maximum = 1.
PAGE 603
ATSAM4L8/L4/L2 – This error is generated if no valid message appears within the TFrame_Maximum time frame slot, while the USART is expecting a response from another node (NACT=SUBSCRIBE). • Checksum Error (CSR.LINCE) – This error is generated if the received checksum is wrong. This error can only be generated if the checksum feature is enabled (CHKDIS=0). • Identifier Parity Error (CSR.LINIPE) – This error is generated if the identifier parity is wrong.
PAGE 604
ATSAM4L8/L4/L2 Figure 24-34. Master Node Configuration, LINMR.NACT is 0x0 (PUBLISH) Frame slot = TFrame_Maximum Frame Header Break Synch Data3 Interframe space Response space Protected Identifier Response Data 1 Data N-1 Data N Checksum TXRDY FSDIS=1 FSDIS=0 RXRDY Write LINIR Write THR Data 1 Data 2 Data 3 Data N LINTC Figure 24-35. Master Node Configuration, LINMR.
PAGE 605
ATSAM4L8/L4/L2 Figure 24-36. Master Node Configuration, LINMR.NACT is 0x2 (IGNORE) Frame slot = TFrame_Maximum Frame Break Interframe space Response space Header Data3 Synch Protected Identifier Response Data 1 Data N-1 Data N Checksum TXRDY FSDIS=1 FSDIS=0 RXRDY Write LINIR LINTC 24.6.11.2 Slave Node Configuration • Configure the baud rate by writing to BRGR.CD and BRGR.
PAGE 606
ATSAM4L8/L4/L2 Figure 24-38. Slave Node Configuration, LINMR.NACT is 0x1 (SUBSCRIBE) Break Synch Protected Identifier Data 1 Data N-1 Data N Checksum TXRDY RXRDY LINIDRX Read LINID Read RHR Data 1 Data N-2 Data N-1 Data N LINTC Figure 24-39. Slave Node Configuration, LINMR.NACT is 0x2 (IGNORE) Break Synch Protected Identifier Data 1 Data N-1 Data N Checksum TXRDY RXRDY LINIDRX Read LINID Read RHR LINTC 24.6.12 24.6.12.
PAGE 607
ATSAM4L8/L4/L2 Figure 24-40. Master Node with Peripheral DMA Controller (LINMR.PDCM=0) WRITE BUFFER DATA 0 Peripheral bus DATA 1 NODE ACTION = SUBSCRIBE Peripheral bus READ BUFFER Peripheral DMA Controller | | | | NODE ACTION = PUBLISH USART LIN CONTROLLER DATA 0 RXRDY Peripheral DMA Controller RXRDY USART LIN CONTROLLER TXRDY | | | | DATA N DATA N Figure 24-41. Master Node with Peripheral DMA Controller (LINMR.
PAGE 608
ATSAM4L8/L4/L2 Figure 24-42. Slave Node with Peripheral DMA Controller WRITE BUFFER READ BUFFER DATA 0 DATA 0 Peripheral bus | | | | | | | | USART LIN CONTROLLER Peripheral DMA Controller Peripheral DMA Controller TXRDY USART LIN CONTROLLER RXRDY DATA N 24.6.13 NACT = SUBSCRIBE Peripheral Bus DATA N Wake-up Request Any node in a sleeping LIN cluster may request a wake-up. By writing to the Wakeup Signal Type bit (LINMR.WKUPTYP), the user can choose to send either a LIN 1.
PAGE 609
ATSAM4L8/L4/L2 select (NSS) signal has been raised by the master. The USART can only generate one NSS signal, and it is possible to use standard I/O lines to address more than one slave. 24.6.15.1 Modes of Operation The SPI system consists of two data lines and two control lines: • Master Out Slave In (MOSI): This line supplies the data shifted from master to slave. In master mode this is connected to TXD, and in slave mode to RXD.
PAGE 610
ATSAM4L8/L4/L2 ter/slave pair must use the same configuration, and the master must be reconfigured if it is to communicate with slaves using different configurations. See Figures 24-43 and 24-44. Table 24-16. SPI Bus Protocol Modes MR.CPOL MR.CPHA SPI Bus Protocol Mode 0 1 0 0 0 1 1 1 2 1 0 3 Figure 24-43.
PAGE 611
ATSAM4L8/L4/L2 24.6.15.4 Receiver and Transmitter Control See ”Manchester Encoder” on page 611, and ”Receiver Status” on page 581. 24.6.15.5 Character Transmission and Reception When the Inhibit Non Acknowledge bit in MR (MR.INACK) is one, the SPI master will not send pending THR values until CSR.RXRDY is zero. In SPI master mode, the slave select line (NSS) is asserted low one bit period before the start of transmission, and released high one bit period after every character transmission.
PAGE 612
ATSAM4L8/L4/L2 1 to 15 bit periods. If the preamble length is zero, the preamble waveform is not generated. The preamble length is selected by writing to the Transmitter Preamble Length field (MAN.TX_PL). The available preamble sequence patterns are: • ALL_ONE • ALL_ZERO • ONE_ZERO • ZERO_ONE and are selected by writing to the Transmitter Preamble Pattern field (MAN.TX_PP). Figure 2446 illustrates the supported patterns. Figure 24-46.
PAGE 613
ATSAM4L8/L4/L2 Figure 24-47. Start Frame Delimiter Preamble Length is set to 0 SFD Manchester encoded data DATA Txd One bit start frame delimiter SFD Manchester encoded data DATA Txd Command Sync start frame delimiter SFD Manchester encoded data DATA Txd Data Sync start frame delimiter Manchester Drift Compensation The Drift Compensation bit (MAN.DRIFT) enables a hardware drift compensation and recovery system that allows for sub-optimal clock drifts without further user intervention.
PAGE 614
ATSAM4L8/L4/L2 The Manchester endec uses the same Start Frame Delimiter Selector (MR.ONEBIT) for both encoder and decoder. If ONEBIT is one, only a Manchester encoded zero will be accepted as a valid start frame delimiter. If ONEBIT is zero, a data or command sync pattern will be expected. The Received Sync bit in the Receive Holding Register (RHR.RXSYNH) will be zero if the last character received is a data sync, and a one if it is a command sync. Figure 24-49.
PAGE 615
ATSAM4L8/L4/L2 Figure 24-51. Manchester Error Preamble Length is set to 4 Elementary character bit time SFD Manchester encoded data Txd Entering USART character area sampling points Preamble subpacket and Start Frame Delimiter were successfully decoded 24.6.16.3 Manchester Coding Error detected Radio Interface: Manchester Endec Application This section describes low data rate, full duplex, dual frequency, RF systems integrated with a Manchester endec, that support ASK and/or FSK modulation schemes.
PAGE 616
ATSAM4L8/L4/L2 Figure 24-53. ASK Modulator Output 1 0 0 1 NRZ stream Manchester encoded data default polarity unipolar output Txd ASK Modulator Output Uptstream Frequency F0 Figure 24-54. FSK Modulator Output 1 0 0 1 NRZ stream Manchester encoded data default polarity unipolar output Txd FSK Modulator Output Uptstream Frequencies [F0, F0+offset] 24.6.
PAGE 617
ATSAM4L8/L4/L2 Figure 24-56. Automatic Echo Mode Configuration RXD Receiver TXD Transmitter 24.6.17.3 Local Loopback Mode Local loopback mode connects the output of the transmitter directly to the input of the receiver, as shown in Figure 24-57. The TXD and RXD pins are not used. The RXD pin has no effect on the receiver and the TXD pin is continuously driven high, as in idle state. Figure 24-57. Local Loopback Mode Configuration RXD Receiver 1 Transmitter 24.6.17.
PAGE 618
ATSAM4L8/L4/L2 7 PARE 6 FRAME 5 OVRE 4 – 3 – 2 RXBRK 1 TXRDY 0 RXRDY The USART has the following interrupt sources: • LINHTE: LIN Header Time-out Error – A LIN Header Time-out Error has been detected • LINSTE: LIN Sync Tolerance Error – A LIN Sync Tolerance Error has been detected • LINSNRE: LIN Slave Not Responding Error – A LIN Slave Not Responding Error has been detected • LINCE: LIN Checksum Error – A LIN Checksum Error has been detected • LINIPE: LIN Identifier Parity Error – A LIN Identifier P
PAGE 619
ATSAM4L8/L4/L2 – If USART operates in SPI slave mode: At least one SPI underrun error has occurred since the last RSTSTA. • TXEMPTY: Transmitter Empty – There are no characters in neither THR, nor in the transmit shift register. • TIMEOUT: Receiver Time-out – There has been a time-out since the last Start Time-out command. • PARE: Parity Error – Either at least one parity error has been detected, or the parity bit is a one in multidrop mode, since the last RSTSTA.
PAGE 620
ATSAM4L8/L4/L2 • ”Baud Rate Generator Register” on page 635 • ”Receiver Time-out Register” on page 637 • ”Transmitter Timeguard Register” on page 638 • ”FI DI Ratio Register” on page 639 • ”IrDA Filter Register” on page 641 • ”Manchester Configuration Register” on page 642 620 42023E–SAM–07/2013
PAGE 621
ATSAM4L8/L4/L2 24.7 User Interface Table 24-17.
PAGE 622
ATSAM4L8/L4/L2 24.7.1 Name: Control Register CR Access Type: Write-only Offset: 0x00 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 LINWKUP 20 LINABT 19 RTSDIS/RCS 18 RTSEN/FCS 17 DTRDIS– 16 DTREN– 15 RETTO 14 RSTNACK 13 RSTIT 12 SENDA 11 STTTO 10 STPBRK 9 STTBRK 8 RSTSTA 7 TXDIS 6 TXEN 5 RXDIS 4 RXEN 3 RSTTX 2 RSTRX 1 – 0 – • LINWKUP: Send LIN Wakeup Signal Writing a zero to this bit has no effect.
PAGE 623
ATSAM4L8/L4/L2 • SENDA: Send Address Writing a zero to this bit has no effect. Writing a one to this bit will in multidrop mode send the next character written to THR as an address. • STTTO: Start Time-out Writing a zero to this bit has no effect. Writing a one to this bit will abort any current time-out count down, and trigger a new count down when the next character has been received. CSR.TIMEOUT is also cleared. • STPBRK: Stop Break Writing a zero to this bit has no effect.
PAGE 624
ATSAM4L8/L4/L2 24.7.2 Name: Mode Register MR Access Type: Read-write Offset: 0x04 Reset Value: 0x00000000 31 ONEBIT 30 MODSYNC 29 MAN 28 FILTER 27 – 26 25 MAX_ITERATION 24 23 INVDATA 22 VAR_SYNC 21 DSNACK 20 INACK 19 OVER 18 CLKO 17 MODE9 16 MSBF/CPOL 15 14 13 12 11 10 PAR 9 8 SYNC/CPHA 4 3 2 1 0 CHMODE 7 NBSTOP 6 CHRL 5 USCLKS MODE This register can only be written if write protection is disabled in the “Write Protect Mode Register” (WPMR.WPEN is zero).
PAGE 625
ATSAM4L8/L4/L2 1: Oversampling at 8 times the baud rate. • CLKO: Clock Output Select 0: The USART does not drive the CLK pin. 1: The USART drives the CLK pin unless USCLKS selects the external clock. • MODE9: 9-bit Character Length 0: CHRL defines character length. 1: 9-bit character length. • MSBF/CPOL: Bit Order or SPI Clock Polarity If USART does not operate in SPI Mode: MSBF=0: Least Significant Bit is sent/received first. MSBF=1: Most Significant Bit is sent/received first.
PAGE 626
ATSAM4L8/L4/L2 SYNC = 1: USART operates in Synchronous mode. If USART operates in SPI Mode, CPHA determines which edge of CLK causes data to change and which edge causes data to be captured. CPHA is used with CPOL to produce the required clock/data relationship between master and slave devices. CPHA = 0: Data is changed on the leading edge of CLK and captured on the following edge of CLK. CPHA = 1: Data is captured on the leading edge of CLK and changed on the following edge of CLK.
PAGE 627
ATSAM4L8/L4/L2 24.7.
PAGE 628
ATSAM4L8/L4/L2 24.7.
PAGE 629
ATSAM4L8/L4/L2 24.7.
PAGE 630
ATSAM4L8/L4/L2 24.7.
PAGE 631
ATSAM4L8/L4/L2 • CTS/LINBLS: Image of CTS Input, or LIN Bus Line Status (when in LIN mode) 0: CTS or LIN Bus Line is low. 1: CTS or LIN Bus Line is high. • DCD: Image of DCD Input 0: DCD is low. 1: DCD is high. • DSR: Image of DSR Input 0: DSR is low. 1: DSR is high. • RI: Image of RI Input 0: RI is low. 1: RI is high. • CTSIC: Clear to Send Input Change Flag 0: No change has been detected on the CTS pin since the last CSR read.
PAGE 632
ATSAM4L8/L4/L2 • TXEMPTY: Transmitter Empty 0: The transmitter is either disabled or there are characters in THR, or in the transmit shift register. 1: There are no characters in neither THR, nor in the transmit shift register. This bit is cleared by writing a one to CR.STTBRK. • TIMEOUT: Receiver Time-out 0: There has not been a time-out since the last Start Time-out command (CR.STTTO), or RTOR.TO is zero. 1: There has been a time-out since the last Start Time-out command.
PAGE 633
ATSAM4L8/L4/L2 24.7.7 Name: Receiver Holding Register RHR Access Type: Read-only Offset: 0x18 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 RXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 RXCHR[8] 7 6 5 4 3 2 1 0 RXCHR[7:0] Reading this register will clear the CSR.RXRDY bit. • RXSYNH: Received Sync 0: Last character received is a data sync. 1: Last character received is a command sync.
PAGE 634
ATSAM4L8/L4/L2 24.7.8 Name: Transmitter Holding Register THR Access Type: Write-only Offset: 0x1C Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 TXCHR[8] 7 6 5 4 3 2 1 0 TXCHR[7:0] • TXSYNH: Sync Field to be transmitted 0: If MR.VARSYNC is one, the next character sent is encoded as data, and the start frame delimiter is a data sync. 1: If MR.
PAGE 635
ATSAM4L8/L4/L2 24.7.9 Name: Baud Rate Generator Register BRGR Access Type: Read-write Offset: 0x20 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 17 FP 16 15 14 13 12 11 10 9 8 3 2 1 0 CD[15:8] 7 6 5 4 CD[7:0] This register can only be written if write protection is disabled in the “Write Protect Mode Register” (WPMR.WPEN is zero). • FP: Fractional Part 0: Fractional divider is disabled.
PAGE 636
ATSAM4L8/L4/L2 Table 24-26.
PAGE 637
ATSAM4L8/L4/L2 24.7.10 Name: Receiver Time-out Register RTOR Access Type: Read-write Offset: 0x24 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 TO[16] 15 14 13 12 11 10 9 8 3 2 1 0 TO[15:8] 7 6 5 4 TO[7:0] This register can only be written if write protection is disabled in the “Write Protect Mode Register” (WPMR.WPEN is zero). • TO: Time-out Value 0: The receiver Time-out is disabled.
PAGE 638
ATSAM4L8/L4/L2 24.7.11 Name: Transmitter Timeguard Register TTGR Access Type: Read-write Offset: 0x28 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 TG This register can only be written if write protection is disabled in the “Write Protect Mode Register” (WPMR.WPEN is zero). • TG: Timeguard Value 0: The transmitter Timeguard is disabled.
PAGE 639
ATSAM4L8/L4/L2 24.7.12 Name: FI DI Ratio Register FIDI Access Type: Read-write Offset: 0x40 Reset Value: 0x00000174 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 9 FI_DI_RATIO[10:8] 8 7 6 5 4 3 FI_DI_RATIO[7:0] 2 1 0 This register can only be written if write protection is disabled in the “Write Protect Mode Register” (WPMR.WPEN is zero).
PAGE 640
ATSAM4L8/L4/L2 24.7.13 Name: Number of Errors Register NER Access Type: Read-only Offset: 0x44 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 NB_ERRORS • NB_ERRORS: Number of Errors Total number of errors that occurred during an ISO7816 transfer. This register is automatically cleared when read.
PAGE 641
ATSAM4L8/L4/L2 24.7.14 Name: IrDA Filter Register IFR Access Type: Read-write Offset: 0x4C Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 IRDA_FILTER This register can only be written if write protection is disabled in the “Write Protect Mode Register” (WPMR.WPEN is zero). • IRDA_FILTER: IrDA Filter Configures the IrDA demodulator filter.
PAGE 642
ATSAM4L8/L4/L2 24.7.15 Name: Manchester Configuration Register MAN Access Type: Read-write Offset: 0x50 Reset Value: 0x30011004 31 – 30 DRIFT 29 1 28 RX_MPOL 27 – 26 – 25 23 – 22 – 21 – 20 – 19 18 17 15 – 14 – 13 – 12 TX_MPOL 11 – 10 – 7 – 6 – 5 – 4 – 3 2 24 RX_PP 16 RX_PL 9 8 TX_PP 1 0 TX_PL This register can only be written if write protection is disabled in the “Write Protect Mode Register” (WPMR.WPEN is zero).
PAGE 643
ATSAM4L8/L4/L2 • TX_PP: Transmitter Preamble Pattern Table 24-28. TX_PP Preamble Pattern default polarity assumed (TX_MPOL field not set) 0 0 ALL_ONE 0 1 ALL_ZERO 1 0 ZERO_ONE 1 1 ONE_ZERO • TX_PL: Transmitter Preamble Length 0: The transmitter preamble pattern generation is disabled. 1 - 15: The preamble length is TX_PL bit periods.
PAGE 644
ATSAM4L8/L4/L2 24.7.16 Name: LIN Mode Register LINMR Access Type: Read-write Offset: 0x54 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 SYNCDIS 16 PDCM 15 14 13 12 11 10 9 8 3 CHKDIS 2 PARDIS 1 DLC 7 WKUPTYP 6 FSDIS 5 DLM 4 CHKTYP 0 NACT • SYNCDIS: Synchronization Disable 0: LIN slave synchronization is enabled. 1: LIN slave synchronization is disabled.
PAGE 645
ATSAM4L8/L4/L2 • NACT: LIN Node Action Table 24-29. NACT Mode Description 0 0 PUBLISH: The USART transmits the response. 0 1 SUBSCRIBE: The USART receives the response. 1 0 IGNORE: The USART does not transmit and does not receive the response.
PAGE 646
ATSAM4L8/L4/L2 24.7.17 Name: LIN Identifier Register LINIR Access Type: Read-write or Read-only Offset: 0x58 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 IDCHR • IDCHR: Identifier Character If USART is in LIN master mode, the IDCHR field is read-write, and its value is the Identifier character to be transmitted.
PAGE 647
ATSAM4L8/L4/L2 24.7.
PAGE 648
ATSAM4L8/L4/L2 24.7.19 Write Protect Mode Register Register Name: WPMR Access Type: Read-write Offset: 0xE4 Reset Value: See Table 24-17 31 30 29 28 27 WPKEY[23:16] 26 25 24 23 22 21 20 19 18 17 16 11 10 9 8 3 - 2 - 1 - 0 WPEN WPKEY[15:8] 15 14 13 12 WPKEY[7:0] 7 - 6 - 5 - 4 - • WPKEY: Write Protect KEY Has to be written to 0x555341 (“USA” in ASCII) in order to successfully write WPEN. This bit always reads as zero. Writing the correct key to this field clears WPSR.
PAGE 649
ATSAM4L8/L4/L2 24.7.20 Write Protect Status Register Register Name: WPSR Access Type: Read-only Offset: 0xE8 Reset Value: See Table 24-17 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 22 21 20 19 WPVSRC[15:8] 18 17 16 15 14 13 12 11 10 9 8 3 - 2 - 1 - 0 WPVS WPVSRC[7:0] 7 - 6 - 5 - 4 - • WPVSRC: Write Protect Violation Source If WPVS is one, this field indicates which write-protected register was unsuccessfully written to, either by address offset or code.
PAGE 650
ATSAM4L8/L4/L2 24.7.21 Version Register Name: VERSION Access Type: Read-only Offset: 0xFC Reset Value: - 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 18 17 16 15 - 14 - 13 - 12 - 11 10 9 VERSION[11:8] 8 7 6 5 4 3 2 0 MFN 1 VERSION[7:0] • MFN Reserved. No functionality associated. • VERSION Version of the module. No functionality associated.
PAGE 651
ATSAM4L8/L4/L2 24.8 Module Configuration The specific configuration for each USART instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Refer to the Power Manager chapter for details. Table 24-30.
PAGE 652
ATSAM4L8/L4/L2 25. Picopower UART (PICOUART) Rev: 1.0.1.0 25.1 Features • Ultra low power UART RX line with fixed format : – 9600 bauds – 1 start bit – 8-bit data – No parity bit – 1 stop bit • Use very low power 32kHz or 1kHz reference clock (Internal RC or Crystal) • Event system support and device wake-up source – start bit detection – full frame reception – character recognition • All low power modes supported included backup mode 25.
PAGE 653
ATSAM4L8/L4/L2 25.4 I/O Lines Description Table 25-1. 25.5 I/O Lines Description Pin Name Pin Description Type RXD Receive Serial Data Input Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 25.5.1 I/O Lines The PICOUART pin is directly connected to the RXD pin, meaning the user doesn’t need to configure the I/O Controller to give control of the pin to the PICOUART. 25.5.
PAGE 654
ATSAM4L8/L4/L2 • One Stop bit • No parity bit A frame is valid when it matches exactly with this configuration. Valid received byte is extracted from the frame and stored in the Receive Holding Register (RHR.CDATA). When a valid data byte is stored, the Data Ready bit is set to one in the Status Register (SR.DRDY). DRDY is set to zero when a new start bit is detected. There is no overrun detection, meaning that RHR value is valid only when DRDY is equal to one. 25.6.
PAGE 655
ATSAM4L8/L4/L2 Figure 25-2. Frame Valid Waveform CLK32 RXD LSB MSB SR.
PAGE 656
ATSAM4L8/L4/L2 25.7 User Interface Table 25-2. Note: PICOUART Register Memory Map Offset Register Register Name Access Reset 0x00 Control Register CR Write-only 0x00000000 0x04 Configuration Register CFG Read/Write 0x00000000 0x08 Status Register SR Read-only 0x00000000 0x0C Receive Holding Register RHR Read 0x00000000 0x20 Version Register VERSION Read-only -(1) 1. The reset values for these registers are device specific.
PAGE 657
ATSAM4L8/L4/L2 25.7.1 Name: Control Register CR Access Type: Write-only Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - DIS EN • DIS: Disable Writing a zero to this bit has no effect. Writing a one to this bit disables PICOUART. This bit always reads as zero.
PAGE 658
ATSAM4L8/L4/L2 25.7.2 Name: Configuration Register CFG Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 1 0 MATCH 7 6 5 4 3 2 - - - - - ACTION SOURCE To avoid unexpected behavior CFG must be written when PICOUART is disabled. • MATCH: Data Match Data used in characterer recognition, only used when SOURCE = 11.
PAGE 659
ATSAM4L8/L4/L2 25.7.3 Name: Status Register SR Access Type: Read-only Offset: 0x08 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - DRDY EN • DRDY: Data Ready 0: No data is ready in RHR. 1: A new data is ready. This bit is cleared when a new start bit is detected. This bit is set when a valid frame is received.
PAGE 660
ATSAM4L8/L4/L2 25.7.
PAGE 661
ATSAM4L8/L4/L2 25.7.5 Name: Version Register VERSION Access Type: Read-only Offset: 0x20 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
PAGE 662
ATSAM4L8/L4/L2 25.8 Module Configuration The specific configuration for each PICOUART instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Refer to Section 10. ”Power Manager (PM)” on page 108 for details. Table 25-3. PICOUART Clocks Module Name Clock Name Description PICOUART CLK_PICOUART Peripheral Clock for PICOUART Table 25-4.
PAGE 663
ATSAM4L8/L4/L2 26. Serial Peripheral Interface (SPI) Rev: 2.1.1.3 26.
PAGE 664
ATSAM4L8/L4/L2 26.3 Block Diagram Figure 26-1. SPI Block Diagram Peripheral DMA Controller Peripheral Bus SPCK MISO CLK_SPI MOSI Spi Interface I/O Controller NPCS0/NSS NPCS1 NPCS2 Interrupt Control NPCS3 SPI Interrupt 26.4 Application Block Diagram Figure 26-2.
PAGE 665
ATSAM4L8/L4/L2 26.5 I/O Lines Description Table 26-1. I/O Lines Description Type 26.6 Pin Name Pin Description Master Slave MISO Master In Slave Out Input Output MOSI Master Out Slave In Output Input SPCK Serial Clock Output Input NPCS1-NPCS3 Peripheral Chip Selects Output Unused NPCS0/NSS Peripheral Chip Select/Slave Select Output Input Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 26.6.
PAGE 666
ATSAM4L8/L4/L2 26.7.2 Data Transfer Four combinations of polarity and phase are available for data transfers. The clock polarity is configured with the Clock Polarity bit in the Chip Select Registers (CSRn.CPOL). The clock phase is configured with the Clock Phase bit in the CSRn registers (CSRn.NCPHA). These two bits determine the edges of the clock signal on which data is driven and sampled.
PAGE 667
ATSAM4L8/L4/L2 Figure 26-4. SPI Transfer Format (NCPHA = 0, 8 bits per transfer) SPCK cycle (for reference) 1 2 3 4 5 6 7 8 SPCK (CPOL = 0) SPCK (CPOL = 1) MOSI (from master) MISO (from slave) *** MSB 6 5 4 3 2 1 MSB 6 5 4 3 2 1 LSB LSB NSS (to slave) *** Not Defined, but normaly LSB of previous character transmitted 26.7.3 Master Mode Operations When configured in master mode, the SPI uses the internal programmable baud rate generator as clock source.
PAGE 668
ATSAM4L8/L4/L2 Figure 26-5 on page 668shows a block diagram of the SPI when operating in master mode. Figure 26-6 on page 669 shows a flow chart describing how transfers are handled. 26.7.3.1 Master Mode Block Diagram Figure 26-5. Master Mode Block Diagram CSR0..3 SCBR CLK_SPI Baud Rate Generator SPCK SPI Clock RXFIFOEN RDRF OVRES RDR RD CSR0..3 BITS NCPHA CPOL LSB MISO 0 1 4 – Character FIFO MSB Shift Register MOSI TDR TD TDRE RXFIFOEN RDR CSR0..
PAGE 669
ATSAM4L8/L4/L2 26.7.3.2 Master Mode Flow Diagram Figure 26-6. Master Mode Flow Diagram SPI Enable - NPCS defines the current Chip Select - CSAAT, DLYBS, DLYBCT refer to the fields of the Chip Select Register corresponding to the Current Chip Select - When NPCS is 0xF, CSAAT is 0.
PAGE 670
ATSAM4L8/L4/L2 26.7.3.3 Clock Generation The SPI Baud rate clock is generated by dividing the CLK_SPI , by a value between 1 and 255. This allows a maximum operating baud rate at up to CLK_SPI and a minimum operating baud rate of CLK_SPI divided by 255. Writing the Serial Clock Baud Rate field in the CSRn registers (CSRn.SCBR) to zero is forbidden. Triggering a transfer while CSRn.SCBR is zero can lead to unpredictable results. At reset, CSRn.
PAGE 671
ATSAM4L8/L4/L2 26.7.3.5 Peripheral Selection The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By default, all the NPCS signals are high before and after each transfer.
PAGE 672
ATSAM4L8/L4/L2 to an interrupt, and thus might lead to difficulties for interfacing with some serial peripherals requiring the chip select line to remain active during a full set of transfers. To facilitate interfacing with such devices, the CSRn registers can be configured with the Chip Select Active After Transfer bit written to one (CSRn.CSAAT) . This allows the chip select lines to remain in their current state (low = active) until transfer to another peripheral is required. When the CSRn.
PAGE 673
ATSAM4L8/L4/L2 Figure 26-8. Peripheral Deselection CSAAT = 0 and CSNAAT = 0 TDRE CSAAT = 1 and CSNAAT= 0 / 1 DLYBCT NPCS[0..3] DLYBCT A A A A DLYBCS A DLYBCS PCS = A PCS = A Write TDR TDRE DLYBCT DLYBCT A NPCS[0..3] A A A DLYBCS A DLYBCS PCS=A PCS = A Write TDR TDRE DLYBCT NPCS[0..3] DLYBCT A B B A DLYBCS DLYBCS PCS = B PCS = B Write TDR CSAAT = 0 and CSNAAT = 0 CSAAT = 0 and CSNAAT = 1 DLYBCT DLYBCT TDRE A NPCS[0..
PAGE 674
ATSAM4L8/L4/L2 register (MR.MODFDIS). In systems with open-drain I/O lines, a mode fault is detected when a low level is driven by an external master on the NPCS0/NSS signal. When a mode fault is detected, the Mode Fault Error bit in the SR (SR.MODF) is set until the SR is read and the SPI is automatically disabled until re-enabled by writing a one to the SPI Enable bit in the CR register (CR.SPIEN). By default, the mode fault detection circuitry is enabled.
PAGE 675
ATSAM4L8/L4/L2 Figure 26-9.
PAGE 676
ATSAM4L8/L4/L2 26.8 User Interface Table 26-3.
PAGE 677
ATSAM4L8/L4/L2 26.8.1 Name: Control Register CR Access Type: Write-only Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - LASTXFER 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - FLUSHFIFO 7 6 5 4 3 2 1 0 SWRST - - - - - SPIDIS SPIEN • LASTXFER: Last Transfer 1: The current NPCS will be deasserted after the character written in TD has been transferred. When CSRn.
PAGE 678
ATSAM4L8/L4/L2 26.8.2 Name: Mode Register MR Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 DLYBCS 23 22 21 20 - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 LLB RXFIFOEN - MODFDIS - PCSDEC PS MSTR PCS • DLYBCS: Delay Between Chip Selects This field defines the delay from NPCS inactive to the activation of another NPCS.
PAGE 679
ATSAM4L8/L4/L2 0: The FIFO is not used in reception (only one character can be stored in the SPI). • MODFDIS: Mode Fault Detection 1: Mode fault detection is disabled. If the I/O controller does not have open-drain capability, mode fault detection must be disabled for proper operation of the SPI. 0: Mode fault detection is enabled. • PCSDEC: Chip Select Decode 0: The chip selects are directly connected to a peripheral device. 1: The four chip select lines are connected to a 4- to 16-bit decoder.
PAGE 680
ATSAM4L8/L4/L2 26.8.3 Name: Receive Data Register RDR Access Type: Read-only Offset: 0x08 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 RD[15:8] 7 6 5 4 RD[7:0] • RD: Receive Data Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero.
PAGE 681
ATSAM4L8/L4/L2 26.8.4 Name: Transmit Data Register TDR Access Type: Write-only Offset: 0x0C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - LASTXFER 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 PCS 11 10 9 8 3 2 1 0 TD[15:8] 7 6 5 4 TD[7:0] • LASTXFER: Last Transfer 1: The current NPCS will be deasserted after the character written in TD has been transferred. When CSRn.
PAGE 682
ATSAM4L8/L4/L2 26.8.5 Name: Status Register SR Access Type: Read-only Offset: 0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - SPIENS 15 14 13 12 11 10 9 8 - - - - - UNDES TXEMPTY NSSR 7 6 5 4 3 2 1 0 - - - - OVRES MODF TDRE RDRF • SPIENS: SPI Enable Status 1: This bit is set when the SPI is enabled. 0: This bit is cleared when the SPI is disabled.
PAGE 683
ATSAM4L8/L4/L2 26.8.6 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x14 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - UNDES TXEMPTY NSSR 7 6 5 4 3 2 1 0 - - - - OVRES MODF TDRE RDRF Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
PAGE 684
ATSAM4L8/L4/L2 26.8.7 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x18 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - UNDES TXEMPTY NSSR 7 6 5 4 3 2 1 0 - - - - OVRES MODF TDRE RDRF Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
PAGE 685
ATSAM4L8/L4/L2 26.8.8 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x1C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - UNDES TXEMPTY NSSR 7 6 5 4 3 2 1 0 - - - - OVRES MODF TDRE RDRF 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
PAGE 686
ATSAM4L8/L4/L2 26.8.9 Name: Chip Select Register 0 CSR0 Access Type: Read/Write Offset: 0x30 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CSAAT CSNAAT NCPHA CPOL DLYBCT 23 22 21 20 DLYBS 15 14 13 12 SCBR 7 6 5 BITS 4 • DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select.
PAGE 687
ATSAM4L8/L4/L2 • BITS: Bits Per Transfer The BITS field determines the number of data bits transferred. Reserved values should not be used. BITS Bits Per Transfer 0000 8 0001 9 0010 10 0011 11 0100 12 0101 13 0110 14 0111 15 1000 16 1001 4 1010 5 1011 6 1100 7 1101 Reserved 1110 Reserved 1111 Reserved • CSAAT: Chip Select Active After Transfer 1: The Peripheral Chip Select does not rise after the last transfer is achieved.
PAGE 688
ATSAM4L8/L4/L2 CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices.
PAGE 689
ATSAM4L8/L4/L2 26.8.10 Name: Chip Select Register 1 CSR1 Access Type: Read/Write Offset: 0x34 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CSAAT CSNAAT NCPHA CPOL DLYBCT 23 22 21 20 DLYBS 15 14 13 12 SCBR 7 6 5 BITS 4 • DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select.
PAGE 690
ATSAM4L8/L4/L2 • BITS: Bits Per Transfer The BITS field determines the number of data bits transferred. Reserved values should not be used. BITS Bits Per Transfer 0000 8 0001 9 0010 10 0011 11 0100 12 0101 13 0110 14 0111 15 1000 16 1001 4 1010 5 1011 6 1100 7 1101 Reserved 1110 Reserved 1111 Reserved • CSAAT: Chip Select Active After Transfer 1: The Peripheral Chip Select does not rise after the last transfer is achieved.
PAGE 691
ATSAM4L8/L4/L2 CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices.
PAGE 692
ATSAM4L8/L4/L2 26.8.11 Name: Chip Select Register 2 CSR2 Access Type: Read/Write Offset: 0x38 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CSAAT CSNAAT NCPHA CPOL DLYBCT 23 22 21 20 DLYBS 15 14 13 12 SCBR 7 6 5 BITS 4 • DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select.
PAGE 693
ATSAM4L8/L4/L2 • BITS: Bits Per Transfer The BITS field determines the number of data bits transferred. Reserved values should not be used. BITS Bits Per Transfer 0000 8 0001 9 0010 10 0011 11 0100 12 0101 13 0110 14 0111 15 1000 16 1001 4 1010 5 1011 6 1100 7 1101 Reserved 1110 Reserved 1111 Reserved • CSAAT: Chip Select Active After Transfer 1: The Peripheral Chip Select does not rise after the last transfer is achieved.
PAGE 694
ATSAM4L8/L4/L2 CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices.
PAGE 695
ATSAM4L8/L4/L2 26.8.12 Name: Chip Select Register 3 CSR3 Access Type: Read/Write Offset: 0x3C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CSAAT CSNAAT NCPHA CPOL DLYBCT 23 22 21 20 DLYBS 15 14 13 12 SCBR 7 6 5 BITS 4 • DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select.
PAGE 696
ATSAM4L8/L4/L2 • BITS: Bits Per Transfer The BITS field determines the number of data bits transferred. Reserved values should not be used. BITS Bits Per Transfer 0000 8 0001 9 0010 10 0011 11 0100 12 0101 13 0110 14 0111 15 1000 16 1001 4 1010 5 1011 6 1100 7 1101 Reserved 1110 Reserved 1111 Reserved • CSAAT: Chip Select Active After Transfer 1: The Peripheral Chip Select does not rise after the last transfer is achieved.
PAGE 697
ATSAM4L8/L4/L2 CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices.
PAGE 698
ATSAM4L8/L4/L2 26.8.
PAGE 699
ATSAM4L8/L4/L2 26.8.
PAGE 700
ATSAM4L8/L4/L2 26.8.15 Features Register Register Name: FEATURES Access Type: Read-only Offset: 0xF8 Reset Value: – 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - SWIMPL FIFORIMPL BRPBHSB CSNAATIMPL EXTDEC 15 14 13 12 11 10 9 8 LENNCONF 7 6 5 4 PHZNCONF PHCONF PPNCONF PCONF LENCONF 3 2 1 0 NCS • SWIMPL: Spurious Write Protection Implemented • • • • • • • • 0: Spurious write protection is not implemented.
PAGE 701
ATSAM4L8/L4/L2 • PPNCONF: Polarity Positive if Polarity not Configurable 0: If polarity is not configurable, polarity is negative. 1: If polarity is not configurable, polarity is positive. • PCONF: Polarity Configurable 0: Polarity is not configurable. 1: Polarity is configurable. • NCS: Number of Chip Selects This field indicates the number of chip selects implemented.
PAGE 702
ATSAM4L8/L4/L2 26.8.16 Version Register Register Name: VERSION Access Type: Read-only Offset: 0xFC Reset Value: – 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 MFN 11 10 VERSION[11:8] 7 6 5 4 3 2 1 0 VERSION[7:0] • MFN Reserved. No functionality associated. • VERSION Version number of the module. No functionality associated.
PAGE 703
ATSAM4L8/L4/L2 26.9 Module Configuration The specific configuration for each SPI instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Refer to Section 10. ”Power Manager (PM)” on page 108 for details. Table 26-4. SPI Clock Name Module Name Clock Name Description SPI CLK_SPI Clock for the SPI bus interface Table 26-5.
PAGE 704
ATSAM4L8/L4/L2 27. Two-wire Master Interface (TWIM) Rev: 1.2.0.1 27.1 Features • Compatible with I²C standard • • • • • • 27.2 – Multi-master support – Transfer speeds up to 3.
PAGE 705
ATSAM4L8/L4/L2 Table 27-2 lists the compatibility level of the Atmel Two-wire Master Interface and a full SMBus compatible master. Table 27-2. 27.3 SMBus Standard Atmel TWIM Bus Timeouts Supported Address Resolution Protocol Supported Host Functionality Supported Packet Error Checking Supported List of Abbreviations Table 27-3. 27.
PAGE 706
ATSAM4L8/L4/L2 27.5 Application Block Diagram Figure 27-2. Application Block Diagram VDD Rp Rp TWD TWI Master TWCK Atmel TWI serial EEPROM I2C RTC I2C LCD controller I2C temp sensor Slave 1 Slave 2 Slave 3 Slave 4 Rp: pull-up value as given by the I2C Standard 27.6 I/O Lines Description Table 27-4. I/O Lines Description Pin Name Pin Description TWD Two-wire Serial Data Input/Output TWCK Two-wire Serial Clock Input/Output 27.
PAGE 707
ATSAM4L8/L4/L2 27.7.3 Clocks The clock for the TWIM bus interface (CLK_TWIM) is generated by the Power Manager. It is recommended to disable the TWIM before disabling the clock, to avoid freezing the TWIM in an undefined state. 27.7.4 DMA The TWIM DMA handshake interface is connected to the Peripheral DMA Controller. Using the TWIM DMA functionality requires the Peripheral DMA Controller to be programmed after setting up the TWIM. 27.7.
PAGE 708
ATSAM4L8/L4/L2 27.8 27.8.1 Functional Description Transfer Format The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure 27-4). Each transfer begins with a START condition and terminates with a STOP condition (see Figure 27-4). • A high-to-low transition on the TWD line while TWCK is high defines the START condition.
PAGE 709
ATSAM4L8/L4/L2 27.8.2.1 High-speed-mode After reset and initialization, the TWIM is in Standard-mode, Fast-mode, or Fast-mode Plus (collectively referred to as the F/S-mode). For the TWIM to enter High-speed-mode (HS-mode), the user must write a one to the HS-mode (HS) bit and write a unique 3-bit code to the HS-mode Master Code field (HSMCODE) in the Command Register (CMDR) or/and the Next Command Register (NCMDR).
PAGE 710
ATSAM4L8/L4/L2 period of the TWCK signal. The TWIM enables its current-source pull-up circuit again when all devices have released the TWCK line and the line reaches a HIGH level. 27.8.2.2 Clock Generation When the TWIM is in F/S-mode, theClock Waveform Generator Register (CWGR) is used to control the waveform of the TWCK clock. CWGR must be written so that the desired TWI bus timings are generated. CWGR describes bus timings as a function of cycles of a prescaled clock.
PAGE 711
ATSAM4L8/L4/L2 Figure 27-5. Bus Timing Diagram t HIGH t LOW S t t LOW t HD:STA SU:DAT t HD:DAT t t SU:DAT t 27.8.2.3 SU:STA SU:STO P Sr Setting up and Performing a Transfer Operation of the TWIM is mainly controlled by the Control Register (CR) and the Command Register (CMDR). TWIM status is provided in the Status Register (SR). The following list presents the main steps in a typical communication: 1.
PAGE 712
ATSAM4L8/L4/L2 27.8.3 Master Transmitter Mode A START condition is transmitted and master transmitter mode is initiated when the bus is free and CMDR has been written with START=1 and READ=0. START and SADR+W will then be transmitted. During the address acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to acknowledge the address.
PAGE 713
ATSAM4L8/L4/L2 Figure 27-7. Master Write with Multiple Data Bytes TWD S DADR W A DATAn A DATAn+5 A DATAn+m A P SR.IDLE TXRDY Write THR (DATAn) NBYTES set to n 27.8.4 Write THR (DATAn+1) Write THR (DATAn+m) Last data sent STOP sent automatically (ACK received and NBYTES=0) Master Receiver Mode A START condition is transmitted and master receiver mode is initiated when the bus is free and CMDR has been written with START=1 and READ=1. START and SADR+R will then be transmitted.
PAGE 714
ATSAM4L8/L4/L2 Figure 27-8. Master Read with One Data Byte TWD S DADR R A DATA N P SR.IDLE RXRDY Write START & STOP bit NBYTES set to 1 Read RHR Figure 27-9. Master Read with Multiple Data Bytes TWD S DADR R A DATAn A DATAn+1 DATAn+m-1 A DATAn+m N P SR.IDLE RXRDY Write START + STOP bit NBYTES set to m Read RHR DATAn Read RHR DATAn+m-2 Read RHR DATAn+m-1 Read RHR DATAn+m Send STOP When NBYTES=0 27.8.
PAGE 715
ATSAM4L8/L4/L2 27.8.6 Multi-master Mode More than one master may access the bus at the same time without data corruption by using arbitration. Arbitration starts as soon as two or more masters place information on the bus at the same time, and stops (arbitration is lost) for the master that intends to send a logical one while the other master sends a logical zero. As soon as arbitration is lost by a master, it stops sending data and listens to the bus in order to detect a STOP. The SR.
PAGE 716
ATSAM4L8/L4/L2 Figure 27-11. Arbitration Cases TWCK TWD TWCK Data from a Master S 1 0 0 1 1 Data from TWI S 1 0 TWD S 1 0 0 1 P Arbitration is lost TWI stops sending data Data from the master 1 1 P Arbitration is lost S 1 0 S 1 0 0 1 1 S 1 0 1 1 The master stops sending data 0 1 Data from the TWI ARBLST Bus is busy Transfer is kept TWI DATA transfer A transfer is programmed (DADR + W + START + Write THR) 27.8.
PAGE 717
ATSAM4L8/L4/L2 6. Wait until SR.TXRDY==1, then write fourth data byte to transfer to THR. 27.8.7.2 Read Followed by Read Consider the following transfer: START, DADR+R, DATA+A, DATA+NA, REPSTART, DADR+R, DATA+A, DATA+NA, STOP. To generate this transfer: 1. Write CMDR with START=1, STOP=0, DADR, NBYTES=2 and READ=1. 2. Write NCMDR with START=1, STOP=1, DADR, NBYTES=2 and READ=1. 3. Wait until SR.RXRDY==1, then read first data byte received from RHR. 4. Wait until SR.
PAGE 718
ATSAM4L8/L4/L2 Figure 27-13. Combining a Read and Write Transfer THR DATA2 RHR TWD DATA0 DATA3 DATA3 1 S SADR R A A DATA0 DATA1 A Sr DADR W A DATA2 A DATA3 NA SR.IDLE P 2 TXRDY Read TWI_RHR RXRDY To generate this transfer: 1. Write CMDR with START=1, STOP=0, DADR, NBYTES=2 and READ=1. 2. Write NCMDR with START=1, STOP=1, DADR, NBYTES=2 and READ=0. 3. Wait until SR.RXRDY==1, then read first data byte received from RHR. 4. Wait until SR.
PAGE 719
ATSAM4L8/L4/L2 1. Write CMDR with TENBIT=1, REPSAME=0, READ=0, START=1, STOP=0, NBYTES=0 and the desired address. 2. Write NCMDR with TENBIT=1, REPSAME=1, READ=1, START=1, STOP=1 and the desired address and NBYTES value. Figure 27-15. A Read Transfer with 10-bit Addressing 1 S 27.8.
PAGE 720
ATSAM4L8/L4/L2 In combined transfers, the PECEN bit should only be written to one in the last of the combined transfers. Consider the following transfer: S, ADR+W, COMMAND_BYTE, ACK, SR, ADR+R, DATA_BYTE, ACK, PEC_BYTE, NACK, P This transfer is generated by writing two commands to the command registers. The first command is a write with NBYTES=1 and PECEN=0, and the second is a read with NBYTES=2 and PECEN=1. Writing a one to the STOP bit in CR will place a STOP condition on the bus after the current byte.
PAGE 721
ATSAM4L8/L4/L2 Table 27-5. Bus Events Event Effect Master transmitter receives SMBus PEC Error SR.DNAK is set. SR.CCOMP not set. CMDR.VALID remains set. STOP automatically transmitted on bus. Master receiver discovers SMBus PEC Error SR.PECERR is set. SR.CCOMP not set. CMDR.VALID remains set. STOP automatically transmitted on bus. CR.STOP is written by user SR.STOP is set. SR.CCOMP set. CMDR.VALID remains set. STOP transmitted on bus after current byte transfer has finished.
PAGE 722
ATSAM4L8/L4/L2 27.9 User Interface Table 27-6.
PAGE 723
ATSAM4L8/L4/L2 27.9.1 Name: Control Register CR Access Type: Write-only Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - STOP 7 6 5 4 3 2 1 0 SWRST - SMDIS SMEN - - MDIS MEN • STOP: Stop the Current Transfer Writing a one to this bit terminates the current transfer, sending a STOP condition after the shifter has become idle.
PAGE 724
ATSAM4L8/L4/L2 27.9.2 Name: Clock Waveform Generator Register CWGR Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 31 30 - 23 29 28 27 26 EXP 22 21 25 24 DATA 20 19 18 17 16 11 10 9 8 3 2 1 0 STASTO 15 14 13 12 HIGH 7 6 5 4 LOW • EXP: Clock Prescaler Used to specify how to prescale the TWCK clock.
PAGE 725
ATSAM4L8/L4/L2 27.9.3 Name: SMBus Timing Register SMBTR Access Type: Read/Write Offset: 0x08 Reset Value: 0x00000000 31 30 29 28 EXP 23 22 21 20 27 26 25 24 - - - - 19 18 17 16 11 10 9 8 3 2 1 0 THMAX 15 14 13 12 TLOWM 7 6 5 4 TLOWS • EXP: SMBus Timeout Clock Prescaler Used to specify how to prescale the TIM and TLOWM counters in SMBTR.
PAGE 726
ATSAM4L8/L4/L2 27.9.4 Name: Command Register CMDR Access Type: Read/Write Offset: 0x0C Reset Value: 0x00000000 31 30 - 23 29 28 HSMCODE 22 21 20 27 26 25 24 - HS ACKLAST PECEN 19 18 17 16 10 9 8 NBYTES 15 14 13 12 11 VALID STOP START REPSAME TENBIT 7 6 5 4 3 SADR[6:0] SADR[9:7] 2 1 0 READ • HSMCODE: HS-mode Master Code 3-bit code to be prefixed with 0b00001 to form a unique 8-bit HS-mode master code (0000 1XXX).
PAGE 727
ATSAM4L8/L4/L2 • • • • 1: The transfer in CMDR should commence with a START or REPEATED START condition. If the bus is free when the command is executed, a START condition is used. If the bus is busy, a REPEATED START is used. REPSAME: Transfer is to Same Address as Previous Address Only used in 10-bit addressing mode, always write to 0 in 7-bit addressing mode.
PAGE 728
ATSAM4L8/L4/L2 27.9.5 Name: Next Command Register NCMDR Access Type: Read/Write Offset: 0x10 Reset Value: 0x00000000 31 30 - 29 28 HSMCODE 23 22 21 20 27 26 25 24 - HS ACKLAST PECEN 19 18 17 16 10 9 8 NBYTES 15 14 13 12 11 VALID STOP START REPSAME TENBIT 7 6 5 4 3 SADR[6:0] SADR[9:7] 2 1 0 READ This register is identical to CMDR. When the VALID bit in CMDR becomes 0, the content of NCMDR is copied into CMDR, clearing the VALID bit in NCMDR.
PAGE 729
ATSAM4L8/L4/L2 27.9.6 Name: Receive Holding Register RHR Access Type: Read-only Offset: 0x14 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 RXDATA • RXDATA: Received Data When the RXRDY bit in the Status Register (SR) is one, this field contains a byte received from the TWI bus.
PAGE 730
ATSAM4L8/L4/L2 27.9.7 Name: Transmit Holding Register THR Access Type: Write-only Offset: 0x18 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 TXDATA • TXDATA: Data to Transmit Write data to be transferred on the TWI bus here.
PAGE 731
ATSAM4L8/L4/L2 27.9.
PAGE 732
ATSAM4L8/L4/L2 • IDLE: Master Interface is Idle This bit is one when no command is in progress, and no command waiting to be issued. Otherwise, this bit is cleared. • CCOMP: Command Complete This bit is one when the current command has completed successfully. This bit is zero if the command failed due to conditions such as a NAK receved from slave. This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
PAGE 733
ATSAM4L8/L4/L2 27.9.9 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x20 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - HSMCACK - 15 14 13 12 11 10 9 8 - STOP PECERR TOUT - ARBLST DNAK ANAK 7 6 5 4 3 2 1 0 - - BUSFREE IDLE CCOMP CRDY TXRDY RXRDY Writing a zero to a bit in this register has no effect.
PAGE 734
ATSAM4L8/L4/L2 27.9.10 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x24 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - HSMCACK - 15 14 13 12 11 10 9 8 - STOP PECERR TOUT - ARBLST DNAK ANAK 7 6 5 4 3 2 1 0 - - BUSFREE IDLE CCOMP CRDY TXRDY RXRDY Writing a zero to a bit in this register has no effect.
PAGE 735
ATSAM4L8/L4/L2 27.9.11 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x28 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - HSMCACK - 15 14 13 12 11 10 9 8 - STOP PECERR TOUT - ARBLST DNAK ANAK 7 6 5 4 3 2 1 0 - - BUSFREE IDLE CCOMP CRDY TXRDY RXRDY 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
PAGE 736
ATSAM4L8/L4/L2 27.9.12 Name: Status Clear Register SCR Access Type : Write-only Offset: 0x2C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - HSMCACK - 15 14 13 12 11 10 9 8 - STOP PECERR TOUT - ARBLST DNAK ANAK 7 6 5 4 3 2 1 0 - - - - CCOMP - - - Writing a zero to a bit in this register has no effect.
PAGE 737
ATSAM4L8/L4/L2 27.9.13 Name: Parameter Register PR Access Type: Read-only Offset: 0x30 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - HS • HS: HS-mode 0: High-speed-mode is not supported. 1: High-speed-mode is supported.
PAGE 738
ATSAM4L8/L4/L2 27.9.14 Name: Version Register VR Access Type: Read-only Offset: 0x34 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION [11:8] 3 2 1 0 VERSION [7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
PAGE 739
ATSAM4L8/L4/L2 27.9.15 Name: HS-mode Clock Waveform Generator Register HSCWGR Access Type: Read/Write Offset: 0x38 Reset Value: 0x00000000 31 30 - 29 28 27 26 EXP 23 22 21 25 24 DATA 20 19 18 17 16 11 10 9 8 3 2 1 0 STASTO 15 14 13 12 HIGH 7 6 5 4 LOW This register is identical to CWGR. It is used to generate the TWCK signal during HS-mode transfer.
PAGE 740
ATSAM4L8/L4/L2 27.9.
PAGE 741
ATSAM4L8/L4/L2 27.9.
PAGE 742
ATSAM4L8/L4/L2 27.10 Module Configuration The specific configuration for each TWIM instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Refer to Section 10. ”Power Manager (PM)” on page 108 for details. Table 27-7.
PAGE 743
ATSAM4L8/L4/L2 28. Two-wire Slave Interface (TWIS) Rev: 1.4.0.1 28.1 Features • Compatible with I²C standard • • • • • • 28.2 – Transfer speeds up to 3.
PAGE 744
ATSAM4L8/L4/L2 Below, Table 28-2 lists the compatibility level of the Atmel Two-wire Slave Interface and a full SMBus compatible device. Table 28-2. 28.3 SMBus Standard Atmel TWIS Bus Timeouts Supported Address Resolution Protocol Supported Packet Error Checking Supported List of Abbreviations Table 28-3. 28.
PAGE 745
ATSAM4L8/L4/L2 28.5 Application Block Diagram Figure 28-2. Application Block Diagram VDD Rp Host with TWI Interface Rp TWD TWCK Atmel TWI serial EEPROM Slave 1 I²C RTC I²C LCD controller I²C temp. sensor Slave 2 Slave 3 Slave 4 Rp: Pull up value as given by the I²C Standard 28.6 I/O Lines Description Table 28-4. I/O Lines Description Pin Name Pin Description TWD Two-wire Serial Data Input/Output TWCK Two-wire Serial Clock Input/Output 28.
PAGE 746
ATSAM4L8/L4/L2 28.7.3 Clocks The clock for the TWIS bus interface (CLK_TWIS) is generated by the Power Manager. It is recommended to disable the TWIS before disabling the clock, to avoid freezing the TWIS in an undefined state. 28.7.4 DMA The TWIS DMA handshake interface is connected to the Peripheral DMA Controller. Using the TWIS DMA functionality requires the Peripheral DMA Controller to be programmed after setting up the TWIS. 28.7.
PAGE 747
ATSAM4L8/L4/L2 28.8.2 Operation The TWIS has two modes of operation: • Slave transmitter mode • Slave receiver mode A master is a device which starts and stops a transfer and generates the TWCK clock. A slave is assigned an address and responds to requests from the master. These modes are described in the following chapters. Figure 28-5. Typical Application Block Diagram VDD Rp Host with TWI Interface Rp TWD TWCK Atmel TWI Serial EEPROM Slave 1 I²C RTC I²C LCD Controller I²C Temp.
PAGE 748
ATSAM4L8/L4/L2 • Write to the relevant register fields in the TWIS with appropriate values and leave those in TWIM as zeros, or vice versa; or • Write to the relevant register fields in both the TWIM and the TWIS with the same values. 28.8.3.1 Bus Timing The Timing Register (TR) is used to control the timing of bus signals driven by the TWIS. TR describes bus timings as a function of cycles of the prescaled CLK_TWIS. The clock prescaling can be selected through TR.EXP.
PAGE 749
ATSAM4L8/L4/L2 28.8.3.2 Setting Up and Performing a Transfer Operation of the TWIS is mainly controlled by the Control Register (CR). The following list presents the main steps in a typical communication: 1. Before any transfers can be performed, bus timings must be configured by writing to the Timing Register (TR) and, if HS-mode transfer is supported, the HS-mode Timing Register (HSTR). 2. If the Peripheral DMA Controller is to be used for the transfers, it must be set up. 3.
PAGE 750
ATSAM4L8/L4/L2 • Module is in slave receiver mode, a byte has been received and placed into the internal shifter, but RHR is full: Discard the received byte and set SR.ORUN. 28.8.3.5 Bus Errors If a bus error (misplaced START or STOP) condition is detected, the SR.BUSERR bit is set and the TWIS waits for a new START condition. 28.8.4 Slave Transmitter Mode If the TWIS matches an address in which the R/W bit in the TWI address phase transfer is set, it will enter slave transmitter mode and set the SR.
PAGE 751
ATSAM4L8/L4/L2 The end of the complete transfer is marked by the SR.TCOMP bit changing from zero to one. See Figure 28-7 and Figure 28-8. Figure 28-7. Slave Transmitter with One Data Byte S TWD DADR R A DATA N P TCOMP TXRDY STOP sent by master Write THR (DATA) NBYTES set to 1 Figure 28-8.
PAGE 752
ATSAM4L8/L4/L2 1. If SMBus mode and PEC is used, NBYTES must be set up with the number of bytes to receive. This is necessary in order to know which of the received bytes is the PEC byte. NBYTES can also be used to count the number of bytes received if using DMA. 2. Receive a byte. Set SR.BTF when done. 3. Update NBYTES. If CR.CUP is written to one, NBYTES is incremented, otherwise NBYTES is decremented. NBYTES is usually configured to count downwards if PEC is used. 4.
PAGE 753
ATSAM4L8/L4/L2 whether to ACK or NAK it. In normal operation of the TWIS, this is not possible because the controller will automatically ACK the byte at about the same time as the RXRDY bit changes from zero to one. Writing a one to the Stretch on Data Byte Received bit (CR.SODR) will stretch the clock allowing the user to update CR.ACK bit before returning the desired value.
PAGE 754
ATSAM4L8/L4/L2 current transfer. The PEC generator is always updated on every bit transmitted or received, so that PEC handling on following linked transfers will be correct. In slave receiver mode, the master calculates a PEC value and transmits it to the slave after all data bytes have been transmitted. Upon reception of this PEC byte, the slave will compare it to the PEC value it has computed itself. If the values match, the data was received correctly, and the slave will return an ACK to the master.
PAGE 755
ATSAM4L8/L4/L2 28.8.10 Identifying Bus Events This chapter lists the different bus events, and how these affects the bits in the TWIS registers. This is intended to help writing drivers for the TWIS. Table 28-5. Bus Events Event Effect Slave transmitter has sent a data byte SR.THR is cleared. SR.BTF is set. The value of the ACK bit sent immediately after the data byte is given by CR.ACK. Slave receiver has received a data byte SR.RHR is set. SR.BTF is set. SR.
PAGE 756
ATSAM4L8/L4/L2 Table 28-5. Bus Events Event Effect Data is to be received in slave receiver mode, SR.STREN is cleared, and RHR is full TWCK is not stretched, read data is discarded. SR.ORUN is set. Data is to be transmitted in slave receiver mode, SR.STREN is cleared, and THR is empty TWCK is not stretched, previous contents of THR is written to bus. SR.URUN is set. SMBus timeout received SR.SMBTOUT is set. TWCK and TWD are immediately released.
PAGE 757
ATSAM4L8/L4/L2 28.9 User Interface Table 28-6.
PAGE 758
ATSAM4L8/L4/L2 28.9.1 Name: Control Register CR Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - TENBIT 23 22 21 20 19 18 17 16 ADR[9:8] ADR[7:0] 15 14 13 12 11 10 9 8 SODR SOAM CUP ACK PECEN SMHH SMDA - 7 6 5 4 3 2 1 0 SWRST - - STREN GCMATCH SMATCH SMEN SEN • TENBIT: Ten Bit Address Match 0: Disables Ten Bit Address Match. 1: Enables Ten Bit Address Match.
PAGE 759
ATSAM4L8/L4/L2 Writing a one to this bit resets the TWIS. • STREN: Clock Stretch Enable 0: Disables clock stretching if RHR/THR buffer full/empty. May cause over/underrun. 1: Enables clock stretching if RHR/THR buffer full/empty. • GCMATCH: General Call Address Match 0: Causes the TWIS not to acknowledge the General Call Address. 1: Causes the TWIS to acknowledge the General Call Address. • SMATCH: Slave Address Match 0: Causes the TWIS not to acknowledge the Slave Address.
PAGE 760
ATSAM4L8/L4/L2 28.9.2 Name: NBYTES Register NBYTES Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 NBYTES • NBYTES: Number of Bytes to Transfer Writing to this field updates the NBYTES counter. The field can also be read to learn the progress of the transfer.
PAGE 761
ATSAM4L8/L4/L2 28.9.3 Name: Timing Register TR Access Type: Read/Write Offset: 0x08 Reset Value: 0x00000000 31 30 29 28 EXP 23 22 21 20 27 26 25 24 - - - - 19 18 17 16 11 10 9 8 3 2 1 0 SUDAT 15 14 13 12 TTOUT 7 6 5 4 TLOWS • EXP: Clock Prescaler Used to specify how to prescale the SMBus TLOWS counter.
PAGE 762
ATSAM4L8/L4/L2 28.9.4 Name: Receive Holding Register RHR Access Type: Read-only Offset: 0x0C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 RXDATA • RXDATA: Received Data Byte When the RXRDY bit in the Status Register (SR) is one, this field contains a byte received from the TWI bus.
PAGE 763
ATSAM4L8/L4/L2 28.9.5 Name: Transmit Holding Register THR Access Type: Write-only Offset: 0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 TXDATA • TXDATA: Data Byte to Transmit Write data to be transferred on the TWI bus here.
PAGE 764
ATSAM4L8/L4/L2 28.9.6 Name: Packet Error Check Register PECR Access Type: Read-only Offset: 0x14 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 PEC • PEC: Calculated PEC Value The calculated PEC value. Updated automatically by hardware after each byte has been transferred. Reset by hardware after a STOP condition.
PAGE 765
ATSAM4L8/L4/L2 28.9.7 Name: Status Register SR Access Type: Read-only Offset: 0x18 Reset Value: 0x000000002 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 BTF REP STO SMBDAM SMBHHM - GCM SAM 15 14 13 12 11 10 9 8 - BUSERR SMBPECERR SMBTOUT - - - NAK 7 6 5 4 3 2 1 0 ORUN URUN TRA - TCOMP SEN TXRDY RXRDY • BTF: Byte Transfer Finished This bit is cleared when the corresponding bit in SCR is written to one.
PAGE 766
ATSAM4L8/L4/L2 • SMBTOUT: SMBus Timeout This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when a SMBus timeout has occurred. • NAK: NAK Received This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when a NAK was received from the master during slave transmitter operation. • ORUN: Overrun This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when an overrun has occurred in slave receiver mode.
PAGE 767
ATSAM4L8/L4/L2 28.9.8 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x1C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 BTF REP STO SMBDAM SMBHHM - GCM SAM 15 14 13 12 11 10 9 8 - BUSERR SMBPECERR SMBTOUT - - - NAK 7 6 5 4 3 2 1 0 ORUN URUN - - TCOMP - TXRDY RXRDY Writing a zero to a bit in this register has no effect.
PAGE 768
ATSAM4L8/L4/L2 28.9.9 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x20 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 BTF REP STO SMBDAM SMBHHM - GCM SAM 15 14 13 12 11 10 9 8 - BUSERR SMBPECERR SMBTOUT - - - NAK 7 6 5 4 3 2 1 0 ORUN URUN - - TCOMP - TXRDY RXRDY Writing a zero to a bit in this register has no effect.
PAGE 769
ATSAM4L8/L4/L2 28.9.10 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x24 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 BTF REP STO SMBDAM SMBHHM - GCM SAM 15 14 13 12 11 10 9 8 - BUSERR SMBPECERR SMBTOUT - - - NAK 7 6 5 4 3 2 1 0 ORUN URUN - - TCOMP - TXRDY RXRDY 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
PAGE 770
ATSAM4L8/L4/L2 28.9.11 Name: Status Clear Register SCR Access Type: Write-only Offset: 0x28 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 BTF REP STO SMBDAM SMBHHM - GCM SAM 15 14 13 12 11 10 9 8 - BUSERR SMBPECERR SMBTOUT - - - NAK 7 6 5 4 3 2 1 0 ORUN URUN - - TCOMP - - - Writing a zero to a bit in this register has no effect.
PAGE 771
ATSAM4L8/L4/L2 28.9.12 Name: Parameter Register PR Access Type: Read-only Offset: 0x2C Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - HS • HS: HS-mode 0: High-speed-mode is not supported. 1: High-speed-mode is supported.
PAGE 772
ATSAM4L8/L4/L2 28.9.13 Name: Version Register VR Access Type: Read-only Offset: 0x30 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION [11:8] 3 2 1 0 VERSION [7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
PAGE 773
ATSAM4L8/L4/L2 28.9.14 Name: HS-mode Timing Register HSTR Access Type: Read/Write Offset: 0x34 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 HDDAT 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - - • HDDAT: Data Hold Cycles Non-prescaled clock cycles for data hold count when the TWIS is in HS-mode. Used to time THD_DAT. Data is driven HDDAT cycles after a LOW on TWCK is detected.
PAGE 774
ATSAM4L8/L4/L2 28.9.
PAGE 775
ATSAM4L8/L4/L2 28.9.
PAGE 776
ATSAM4L8/L4/L2 28.10 Module Configuration The specific configuration for each TWIS instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Refer to Section 10. ”Power Manager (PM)” on page 108 for details. Table 28-7. Module Clock Name Module Name Clock Name Description TWIS0 CLK_TWIS0 Clock for the TWIS0 bus interface TWIS1 CLK_TWIS1 Clock for the TWIS1 bus interface Note : TWI2 and TWI3 are master only.
PAGE 777
ATSAM4L8/L4/L2 29. Inter-IC Sound Controller (IISC) Rev: 1.0.0.0 29.1 Features • Compliant with Inter-IC Sound (I2S) bus specification • Master, slave, and controller modes: • • • • • 29.
PAGE 778
ATSAM4L8/L4/L2 29.3 Block Diagram Figure 29-1. IISC Block Diagram IISC Peripheral DMA Controller Interrupt Controller 29.4 Clocks PB clock PB Rx Tx IRQ Transmitter IWS ISDI ISDO I/O Lines Description Table 29-1. I/O Lines Description Pin Name 29.
PAGE 779
ATSAM4L8/L4/L2 29.5.3 Clocks The clock for the IISC bus interface (CLK_IISC) is generated by the Power Manager. It is recommended to disable the IISC before disabling the clock, to avoid freezing the IISC in an undefined state. One of the generic clocks is connected to the IISC. The generic clock (GCLK_IISC) can be set to a wide range of frequencies and clock sources. The GCLK_IISC must be enabled and configured before use.
PAGE 780
ATSAM4L8/L4/L2 The Transmitter can be operated by writing to the Transmitter Holding Register (RHR), whenever the Transmit Ready (TXRDY) bit in the Status Register (SR) is set. Successive values written to THR should correspond to the samples from the left and right audio channels for the successive frames. The Receive Ready and Transmit Ready bits can be polled by reading the Status Register. The IISC processor load can be reduced by enabling interrupt-driven operation.
PAGE 781
ATSAM4L8/L4/L2 29.6.5 Serial Clock and Word Select Generation The generation of clocks in the IISC is described in Figure 29-3 on page 782. In Slave mode, the Serial Clock and Word Select Clock are driven by an external master. ISCK and IWS pins are inputs and no generic clock is required by the IISC. In Master mode, the user can configure the Master Clock, Serial Clock, and Word Select Clock through the Mode Register (MR).
PAGE 782
ATSAM4L8/L4/L2 Figure 29-3. IISC Clocks Generation CR.CKEN/CKDIS MR.IMCKMODE Clock enable GCLK_IISC IMCK pin output Clock divider MR.IMCKMODE 0 MR.IMCKFS MR.DATALENGTH 1 ISCK pin output CR.CKEN/CKDIS 0 ISCK pin input 1 Internal bit clock Clock enable Clock divider MR.MODE = SLAVE MR.DATALENGTH IWS pin output 0 IWS pin input 29.6.
PAGE 783
ATSAM4L8/L4/L2 Data words are right-justified in the RHR and THR registers. For 16-bit compact stereo, the left sample uses bits 15 through 0 and the right sample uses bits 31 through 16 of the same data word. For 8-bit compact stereo, the left sample uses bits 7 through 0 and the right sample uses bits 15 through 8 of the same data word. 29.6.
PAGE 784
ATSAM4L8/L4/L2 Figure 29-4. Interrupt Block Diagram IER Set IMR Clear IDR Transmitter TXRDY TXUR Interrupt Control IISC Interrupt Request Receiver RXRDY RXOR 29.7 IISC Application Examples The IISC can support several serial communication modes used in audio or high-speed serial links. Some standard applications are shown in the following figures. All serial link applications supported by the IISC are not listed here. Figure 29-5.
PAGE 785
ATSAM4L8/L4/L2 Figure 29-6. Codec Application Block Diagram IMCK ISCK IISC Master Clock Serial Clock EXTERNAL AUDIO CODEC Word Select IWS ISDO ISDI Serial Data Out Serial Data In Serial Clock Word Select Right Time Slot Left Time Slot Dstart Dend Serial Data Out Serial Data In Figure 29-7.
PAGE 786
ATSAM4L8/L4/L2 29.8 User Interface Table 29-3.
PAGE 787
ATSAM4L8/L4/L2 29.8.
PAGE 788
ATSAM4L8/L4/L2 29.8.2 Name: Mode Register MR Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 31 30 29 28 IWS24 IMCKMODE 23 22 21 20 - - - 15 14 - 27 26 25 24 19 18 17 16 - - - - - 13 12 11 10 9 8 TXSAME TXDMA TXMONO RXLOOP RXDMA RXMONO 7 6 5 4 2 1 0 - - - - MODE IMCKFS 3 DATALENGTH The Mode Register should only be written when the IISC is stopped, in order to avoid unwanted glitches on the IWS, ISCK, and ISDO outputs.
PAGE 789
ATSAM4L8/L4/L2 Master Clock to Sample Frequency (fs) Ratio Table 29-4. fs Ratio IMCKFS 384 fs 23 512 fs 31 768 fs 47 1024 fs 63 • TXSAME: Transmit Data when Underrun 0: Zero sample transmitted when underrun. 1: Previous sample transmitted when underrun • TXDMA: Single or multiple DMA Channels for Transmitter 0: Transmitter uses a single DMA channel for both audio channels. 1: Transmitter uses one DMA channel per audio channel. • TXMONO: Transmit Mono 0: Stereo.
PAGE 790
ATSAM4L8/L4/L2 29.8.3 Name: Status Register SR Access Type: Read-only Offset: 0x08 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - 15 14 13 12 11 10 9 8 - - - - - - 7 6 5 4 3 2 1 0 - TXUR TXRDY TXEN - RXOR RXRDY RXEN TXURCH RXORCH • TXURCH: Transmit Underrun Channel This field is cleared when SCR.TXUR is written to one.
PAGE 791
ATSAM4L8/L4/L2 29.8.4 Name: Status Clear Register SCR Access Type: Write-only Offset: 0x0C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - 15 14 13 12 11 10 9 8 - - - - - - 7 6 5 4 3 2 1 0 - TXUR - - - RXOR - - TXURCH RXORCH Writing a zero to a bit in this register has no effect.
PAGE 792
ATSAM4L8/L4/L2 29.8.5 Name: Status Set Register SSR Access Type: Write-only Offset: 0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - 15 14 13 12 11 10 9 8 - - - - - - 7 6 5 4 3 2 1 0 - TXUR - - - RXOR - - TXURCH RXORCH Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in SR.
PAGE 793
ATSAM4L8/L4/L2 29.8.6 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x14 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - TXUR TXRDY - - RXOR RXRDY - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
PAGE 794
ATSAM4L8/L4/L2 29.8.7 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x18 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - TXUR TXRDY - - RXOR RXRDY - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
PAGE 795
ATSAM4L8/L4/L2 29.8.8 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x1C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - TXUR TXRDY - - RXOR RXRDY - 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
PAGE 796
ATSAM4L8/L4/L2 29.8.9 Name: Receive Holding Register RHR Access Type: Read-only Offset: 0x20 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RHR[31:24] 23 22 21 20 RHR[23:16] 15 14 13 12 RHR[15:8] 7 6 5 4 RHR[7:0] • RHR: Received Word This field is set by hardware to the last received data word. If MR.DATALENGTH specifies less than 32 bits, data shall be rightjustified into the RHR field.
PAGE 797
ATSAM4L8/L4/L2 29.8.10 Name: Transmit Holding Register THR Access Type: Write-only Offset: 0x24 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 THR[31:24] 23 22 21 20 THR[23:16] 15 14 13 12 THR[15:8] 7 6 5 4 THR[7:0] • THR: Data Word to Be Transmitted Next data word to be transmitted after the current word if TXRDY is not set. If MR.DATALENGTH specifies less than 32 bits, data shall be right-justified into the THR field.
PAGE 798
ATSAM4L8/L4/L2 29.8.11 Name: Module Version VERSION Access Type: Read-only Offset: 0x28 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 1 0 VARIANT 11 10 VERSION[11:8] 3 2 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
PAGE 799
ATSAM4L8/L4/L2 29.8.12 Name: Module Parameters PARAMETER Access Type: Read-only Offset: 0x2C Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - - Reserved. No functionality associated.
PAGE 800
ATSAM4L8/L4/L2 29.9 Module Configuration The specific configuration for each IISC instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Refer to Section 10. ”Power Manager (PM)” on page 108 for details. Table 29-7. IISC Clocks Clock Name Description CLK_IISC Clock for the IISC bus interface GCLK The generic clock used for the IISC is GCLK6 Table 29-8.
PAGE 801
ATSAM4L8/L4/L2 30. Timer/Counter (TC) Rev: 4.0.2.0 30.1 Features • Three 16-bit Timer Counter channels • A wide range of functions including: • • • • • 30.
PAGE 802
ATSAM4L8/L4/L2 30.
PAGE 803
ATSAM4L8/L4/L2 When using the TIOA/TIOB lines as inputs the user must make sure that no peripheral events are generated on the line. Refer to Section 31. ”Peripheral Event Controller (PEVC)” on page 844 for details. 30.5.2 Power Management If the CPU enters a sleep mode that disables clocks used by the TC, the TC will stop functioning and resume operation after the system wakes up from sleep mode. 30.5.3 Clocks The clock for the TC bus interface (CLK_TC) is generated by the Power Manager.
PAGE 804
ATSAM4L8/L4/L2 passes to 0x0000, an overflow occurs and the Counter Overflow Status bit in the Channel n Status Register (SRn.COVFS) is set. The current value of the counter is accessible in real time by reading the Channel n Counter Value Register (CVn). The counter can be reset by a trigger. In this case, the counter value passes to 0x0000 on the next valid edge of the selected clock. 30.6.1.
PAGE 805
ATSAM4L8/L4/L2 Figure 30-1. Clock Selection TCCLKS TIMER_CLOCK1 TIMER_CLOCK2 CLKI TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 Selected Clock XC0 XC1 XC2 BURST 1 30.6.1.4 Clock control The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. See Figure 30-2 on page 806. • The clock can be enabled or disabled by the user by writing to the Counter Clock Enable/Disable Command bits in the Channel n Clock Control Register (CCRn.CLKEN and CCRn.CLKDIS).
PAGE 806
ATSAM4L8/L4/L2 Figure 30-2. Clock Control Selected Clock Trigger CLKSTA Q Q S CLKEN CLKDIS S R R Counter Clock 30.6.1.5 Stop Event Disable Event TC operating modes Each channel can independently operate in two different modes: • Capture mode provides measurement on signals. • Waveform mode provides wave generation. The TC operating mode selection is done by writing to the Wave bit in the CCRn register (CCRn.WAVE). In Capture mode, TIOA and TIOB are configured as inputs.
PAGE 807
ATSAM4L8/L4/L2 The channel can also be configured to have an external trigger. In Capture mode, the external trigger signal can be selected between TIOA and TIOB. In Waveform mode, an external event can be programmed to be one of the following signals: TIOB, XC0, XC1, or XC2. This external event can then be programmed to perform a trigger by writing a one to the External Event Trigger Enable bit in CMRn (CMRn.ENETRG).
PAGE 808
42023E–SAM–07/2013 TIOA TIOB SYNC MTIOA MTIOB TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 TIMER_CLOCK1 1 Edge Detector ETRGEDG SWTRG CLKI Edge Detector LDRA CLK Trig S R OVF If RA is Loaded CPCTRG 16-bit Counter RESET Q LDBSTOP R S CLKEN Edge Detector LDRB Capture Register A Q CLKSTA LDBDIS Capture Register B CLKDIS SR Timer/Counter Channel If RA is not Loaded or RB is Loaded ABETRG BURST TCCLKS Compare RC = Register C COVFS INT ATSAM4L8/L4/L2
PAGE 809
ATSAM4L8/L4/L2 30.6.3 Waveform Operating Mode Waveform operating mode is entered by writing a one to the CMRn.WAVE bit. In Waveform operating mode the TC channel generates one or two PWM signals with the same frequency and independently programmable duty cycles, or generates different types of oneshot or repetitive pulses. In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event.
PAGE 810
42023E–SAM–07/2013 TIOB SYNC XC2 XC1 TIMER_CLOCK5 XC0 TIMER_CLOCK4 TIMER_CLOCK3 TIMER_CLOCK2 TIMER_CLOCK1 1 Edge Detector EEVTEDG SWTRG Timer/Counter Channel EEVT BURST CLKI ENETRG Trig CLK R S WAVSEL RESET 16-bit Counter WAVSEL Q OVF Compare RA = Register A Q CLKSTA Compare RC = Compare RB = CPCSTOP CPCDIS Register C CLKDIS Register B R S CLKEN CPAS INT BSWTRG BEEVT BCPB BCPC ASWTRG AEEVT ACPA ACPC Output Contr oller O utput Cont r oller TCCLKS TIOB MT
PAGE 811
ATSAM4L8/L4/L2 30.6.3.2 WAVSEL = 0 When CMRn.WAVSEL is zero, the value of CVn is incremented from 0 to 0xFFFF. Once 0xFFFF has been reached, the value of CVn is reset. Incrementation of CVn starts again and the cycle continues. See Figure 30-5 on page 811. An external event trigger or a software trigger can reset the value of CVn. It is important to note that the trigger may occur at any time. See Figure 30-6 on page 812. RC Compare cannot be programmed to generate a trigger in this configuration.
PAGE 812
ATSAM4L8/L4/L2 Figure 30-6. WAVSEL= 0 With Trigger Counter Value Counter cleared by compare match with 0xFFFF 0xFFFF RC Counter cleared by trigger RB RA Waveform Examples Time TIOB TIOA 30.6.3.3 WAVSEL = 2 When CMRn.WAVSEL is two, the value of CVn is incremented from zero to the value of RC, then automatically reset on a RC Compare. Once the value of CVn has been reset, it is then incremented and so on. See Figure 30-7 on page 813.
PAGE 813
ATSAM4L8/L4/L2 Figure 30-7. WAVSEL = 2 Without Trigger Counter Value 0xFFFF Counter cleared by compare match with RC RC RB RA Waveform Examples Time TIOB TIOA Figure 30-8. WAVSEL = 2 With Trigger Counter Value 0xFFFF Counter cleared by compare match with RC Counter cleared by trigger RC RB RA Waveform Examples Time TIOB TIOA 30.6.3.4 WAVSEL = 1 When CMRn.WAVSEL is one, the value of CVn is incremented from 0 to 0xFFFF.
PAGE 814
ATSAM4L8/L4/L2 A trigger such as an external event or a software trigger can modify CVn at any time. If a trigger occurs while CVn is incrementing, CVn then decrements. If a trigger is received while CVn is decrementing, CVn then increments. See Figure 30-10 on page 814. RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CMRn.CPCSTOP = 1) and/or disable the counter clock (CMRn.CPCDIS = 1). Figure 30-9.
PAGE 815
ATSAM4L8/L4/L2 30.6.3.5 WAVSEL = 3 When CMRn.WAVSEL is three, the value of CVn is incremented from zero to RC. Once RC is reached, the value of CVn is decremented to zero, then re-incremented to RC and so on. See Figure 30-11 on page 815. A trigger such as an external event or a software trigger can modify CVn at any time. If a trigger occurs while CVn is incrementing, CVn then decrements. If a trigger is received while CVn is decrementing, CVn then increments. See Figure 30-12 on page 816.
PAGE 816
ATSAM4L8/L4/L2 Figure 30-12. WAVSEL = 3 With Trigger Counter Value 0xFFFF Counter decremented by compare match with RC RC Counter decremented by trigger RB Counter incremented by trigger RA Waveform Examples TIOB Time TIOA 30.6.3.6 External event/trigger conditions An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The external event selected can then be used as a trigger. The External Event Selection field in CMRn (CMRn.
PAGE 817
ATSAM4L8/L4/L2 • RB Compare Effect on TIOB (CMRn.BCPB) • RC Compare Effect on TIOA (CMRn.ACPC) • RA Compare Effect on TIOA (CMRn.ACPA) 30.7 2-bit Gray Up/Down Counter for Stepper Motor Each channel can be independently configured to generate a 2-bit gray count waveform on corresponding TIOA, TIOB outputs by means of GCEN bit in SMMRx registers. Up or Down count can be defined by writing bit DOWN in SMMRx registers. It is mandatory to configure the channel in WAVE mode in CMR register.
PAGE 818
ATSAM4L8/L4/L2 30.9 User Interface Table 30-3.
PAGE 819
ATSAM4L8/L4/L2 Table 30-3. TC Register Memory Map Offset Register Register Name Access Reset 0xE4 Write Protect Mode Register WPMR Read/Write 0x00000000 0xF8 Features Register FEATURES Read-only -(2) 0xFC Version Register VERSION Read-only -(2) Notes: 1. Read-only if CMRn.WAVE is zero. 2. The reset values are device specific. Refer to the Module Configuration section at the end of this chapter.
PAGE 820
ATSAM4L8/L4/L2 30.9.1 Name: Channel Control Register CCR Access Type: Write-only Offset: 0x00 + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - SWTRG CLKDIS CLKEN • SWTRG: Software Trigger Command 1: Writing a one to this bit will perform a software trigger: the counter is reset and the clock is started.
PAGE 821
ATSAM4L8/L4/L2 30.9.2 Name: Channel Mode Register: Capture Mode CMR Access Type: Read/Write Offset: 0x04 + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 11 10 WAVE CPCTRG - - - ABETRG 7 6 5 4 3 2 LDBDIS LDBSTOP BURST LDRB LDRA CLKI 9 8 ETRGEDG 1 0 TCCLKS This register can only be written if write protect is disabled (WPMR.WPEN is zero).
PAGE 822
ATSAM4L8/L4/L2 • ABETRG: TIOA or TIOB External Trigger Selection 1: TIOA is used as an external trigger. 0: TIOB is used as an external trigger. • ETRGEDG: External Trigger Edge Selection ETRGEDG Edge 0 none 1 rising edge 2 falling edge 3 each edge • LDBDIS: Counter Clock Disable with RB Loading 1: Counter clock is disabled when RB loading occurs. 0: Counter clock is not disabled when RB loading occurs.
PAGE 823
ATSAM4L8/L4/L2 30.9.3 Name: Channel Mode Register: Waveform Mode CMR Access Type: Read/Write Offset: 0x04 + n * 0x40 Reset Value: 0x00000000 31 30 29 BSWTRG 23 27 BEEVT 22 21 ASWTRG 15 28 20 WAVE 13 7 6 19 CPCDIS CPCSTOP 4 BURST BCPB 18 11 ENETRG 5 24 17 16 ACPC 12 WAVSEL 25 BCPC AEEVT 14 26 ACPA 10 9 EEVT 3 8 EEVTEDG 2 CLKI 1 0 TCCLKS This register can only be written if write protect is disabled (WPMR.WPEN is zero).
PAGE 824
ATSAM4L8/L4/L2 • BCPC: RC Compare Effect on TIOB BCPC Effect 0 none 1 set 2 clear 3 toggle • BCPB: RB Compare Effect on TIOB BCPB Effect 0 none 1 set 2 clear 3 toggle • ASWTRG: Software Trigger Effect on TIOA ASWTRG Effect 0 none 1 set 2 clear 3 toggle • AEEVT: External Event Effect on TIOA AEEVT Effect 0 none 1 set 2 clear 3 toggle • ACPC: RC Compare Effect on TIOA ACPC Effect 0 none 1 set 2 clear 3 toggle 824 42023E–SAM–07/2013
PAGE 825
ATSAM4L8/L4/L2 • ACPA: RA Compare Effect on TIOA ACPA Effect 0 none 1 set 2 clear 3 toggle • WAVE 1: Waveform mode is enabled. 0: Waveform mode is disabled (Capture mode is enabled).
PAGE 826
ATSAM4L8/L4/L2 • CPCSTOP: Counter Clock Stopped with RC Compare 1: Counter clock is stopped when counter reaches RC. 0: Counter clock is not stopped when counter reaches RC. • BURST: Burst Signal Selection BURST Burst Signal Selection 0 The clock is not gated by an external signal. 1 XC0 is ANDed with the selected clock. 2 XC1 is ANDed with the selected clock. 3 XC2 is ANDed with the selected clock. • CLKI: Clock Invert 1: Counter is incremented on falling edge of the clock.
PAGE 827
ATSAM4L8/L4/L2 30.9.4 Name: Stepper Motor Mode Register SMCR Access Type: Read/Write Offset: 0x08 + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - DOWN GCEN This register can only be written if write protect is disabled (WPMR.WPEN is zero). • DOWN: Down Count 0: Up counter. 1: Down counter.
PAGE 828
ATSAM4L8/L4/L2 30.9.5 Name: Channel Counter Value Register CV Access Type: Read-only Offset: 0x10 + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 CV[15:8] 7 6 5 4 CV[7:0] • CV: Counter Value CV contains the counter value in real time.
PAGE 829
ATSAM4L8/L4/L2 30.9.6 Name: Channel Register A RA Access Type: Read-only if CMRn.WAVE = 0, Read/Write if CMRn.WAVE = 1 Offset: 0x14 + n * 0X40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 RA[15:8] 7 6 5 4 RA[7:0] This register can only be written if write protect is disabled (WPMR.WPEN is zero). • RA: Register A RA contains the Register A value in real time.
PAGE 830
ATSAM4L8/L4/L2 30.9.7 Name: Channel Register B RB Access Type: Read-only if CMRn.WAVE = 0, Read/Write if CMRn.WAVE = 1 Offset: 0x18 + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 RB[15:8] 7 6 5 4 RB[7:0] This register can only be written if write protect is disabled (WPMR.WPEN is zero). • RB: Register B RB contains the Register B value in real time.
PAGE 831
ATSAM4L8/L4/L2 30.9.8 Name: Channel Register C RC Access Type: Read/Write Offset: 0x1C + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 RC[15:8] 7 6 5 4 RC[7:0] This register can only be written if write protect is disabled (WPMR.WPEN is zero). • RC: Register C RC contains the Register C value in real time.
PAGE 832
ATSAM4L8/L4/L2 30.9.9 Name: Channel Status Register SR Access Type: Read-only Offset: 0x20 + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - MTIOB MTIOA CLKSTA 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS Note: Reading the Status Register will also clear the interrupt bit for the corresponding interrupts.
PAGE 833
ATSAM4L8/L4/L2 • CPBS: RB Compare Status 1: This bit is set when an RB Compare has occurred and CMRn.WAVE is one. 0: This bit is cleared when the SR register is read. • CPAS: RA Compare Status 1: This bit is set when an RA Compare has occurred and CMRn.WAVE is one. 0: This bit is cleared when the SR register is read. • LOVRS: Load Overrun Status 1: This bit is set when RA or RB have been loaded at least twice without any read of the corresponding register and CMRn.WAVE is zero.
PAGE 834
ATSAM4L8/L4/L2 30.9.10 Name: Channel Interrupt Enable Register IER Access Type: Write-only Offset: 0x24 + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS Writing a zero to a bit in this register has no effect.
PAGE 835
ATSAM4L8/L4/L2 30.9.11 Name: Channel Interrupt Disable Register IDR Access Type: Write-only Offset: 0x28 + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS Writing a zero to a bit in this register has no effect.
PAGE 836
ATSAM4L8/L4/L2 30.9.12 Name: Channel Interrupt Mask Register IMR Access Type: Read-only Offset: 0x2C + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
PAGE 837
ATSAM4L8/L4/L2 30.9.13 Name: Block Control Register BCR Access Type: Write-only Offset: 0xC0 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - SYNC • SYNC: Synchro Command 1: Writing a one to this bit asserts the SYNC signal which generates a software trigger simultaneously for each of the channels.
PAGE 838
ATSAM4L8/L4/L2 30.9.14 Name: Block Mode Register BMR Access Type: Read/Write Offset: 0xC4 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - TC2XC2S TC1XC1S TC0XC0S This register can only be written if write protect is disabled (WPMR.WPEN is zero).
PAGE 839
ATSAM4L8/L4/L2 • TC2XC2S: External Clock Signal 2 Selection TC2XC2S Signal Connected to XC2 0 TCLK2 1 none 2 TIOA0 3 TIOA1 • TC1XC1S: External Clock Signal 1 Selection TC1XC1S Signal Connected to XC1 0 TCLK1 1 none 2 TIOA0 3 TIOA2 • TC0XC0S: External Clock Signal 0 Selection TC0XC0S Signal Connected to XC0 0 TCLK0 1 none 2 TIOA1 3 TIOA2 839 42023E–SAM–07/2013
PAGE 840
ATSAM4L8/L4/L2 30.9.15 Name: Write Protect Mode Register WPMR Access Type: Read/write Offset: 0xE4 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 - - - - - - - WPEN • WPKEY: Write Protect Key Valid key is “TIM” in ASCII (0x54494D in hexadecimal). • WPEN: Write Protect Enable 1: Writing a one to this bit will enable write protection (WPKEY must be set).
PAGE 841
ATSAM4L8/L4/L2 30.9.16 Name: Features Register FEATURES Access Type: Read-only Offset: 0xF8 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - BRPBHSB UPDNIMPL 7 6 5 4 3 2 1 0 CTRSIZE • BRPBHSB: Bridge type is PB to HSB 1: Bridge type is PB to HSB. 0: Bridge type is not PB to HSB. • UPDNIMPL: Up/down is implemented 1: Up/down counter capability is implemented.
PAGE 842
ATSAM4L8/L4/L2 30.9.17 Name: Version Register VERSION Access Type: Read-only Offset: 0xFC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
PAGE 843
ATSAM4L8/L4/L2 30.10 Module Configuration The specific configuration for each Timer/Counter instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Refer to Section 10. ”Power Manager (PM)” on page 108 for details. Table 30-4.
PAGE 844
ATSAM4L8/L4/L2 31. Peripheral Event Controller (PEVC) Rev: 2.0.0.0 31.1 Features • • • • 31.2 Direct peripheral to peripheral communication system Allows peripherals to receive, react to, and send peripheral events without CPU intervention Cycle deterministic event communication SleepWalking™ and asynchronous interrupts for peripheral operation in Power Save Modes Overview Several peripheral modules can be configured to emit or respond to signals known as peripheral events.
PAGE 845
ATSAM4L8/L4/L2 31.
PAGE 846
ATSAM4L8/L4/L2 31.4 I/O Lines Description Table 31-1. 31.5 I/O Lines Description Pin Name Pin Description Type PAD_EVT[n] External Event Inputs Input Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 31.5.1 I/O Lines Multiplexed I/O lines can be used as event generators. To generate a peripheral event from an external source the source pin must be configured as an input pin by the I/O Controller.
PAGE 847
ATSAM4L8/L4/L2 Table 31-2.
PAGE 848
ATSAM4L8/L4/L2 31.5.4 Interrupts PEVC can generate an interrupt request in case of trigger generation or trigger overrun. The PEVC interrupt request lines are connected to the NVIC. Using the PEVC interrupts requires the NVIC to be programmed first. 31.5.5 Debug Operation PEVC is not frozen during debug operation when the Core is halted, unless the bit corresponding to the PEVC is set in the Peripheral Debug Register (PDBG). Refer to the On-Chip Debug chapter for details.
PAGE 849
ATSAM4L8/L4/L2 31.6 Functional Description 31.6.1 31.6.1.1 PEVC Channel Operation PEVC routes incoming events to users by means of one channel per user. Channels operate in parallel, allowing multiple users to listen to the same generator. Channel Setup The Channel Multiplexer Register (CHMXi) is written to allocate a generator to a given channel. The Event Multiplexer field (EVMX) selects between the different generators, while the Software Event Multiplexer bit (SMX) selects Software Events.
PAGE 850
ATSAM4L8/L4/L2 31.6.2 Event Shaper (EVS) Operation PEVC contains Event Shapers (EVS) for certain types of generators: • External inputs • General-purpose waveforms like timer outputs or Generic Clocks Refer to the Module Configuration section at the end of this chapter for the device-specific configuration of Event Shapers and Input Glitch Filters.
PAGE 851
ATSAM4L8/L4/L2 Table 31-3. Event Propagation Latency Generator CHMXi.EVMX Input Glitch Filter EVSj.IGF Latency Clock Software event - 0 - Generator without Event Shaper - 0 - Generator with Event Shaper Off 2 Generator with Event Shaper Asynchronous Generator in SleepWalking™ operation CLK_PEVC IGFDR On 3*2 On or Off unpredicted CLK_RCSYS - Refer to the Module Configuration section at the end of this chapter for the list of generators implementing Event Shapers. 31.
PAGE 852
ATSAM4L8/L4/L2 31.8 User Interface Table 31-4.
PAGE 853
ATSAM4L8/L4/L2 31.8.1 Name: Channel Status Register CHSR Access Type: Read-only Offset: 0x000 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CHS 23 22 21 20 CHS 15 14 13 12 CHS 7 6 5 4 CHS • CHS: Channel Status 0: The corresponding channel is disabled. 1: The corresponding channel is enabled. This bit is cleared when the corresponding bit in CHDR is written to one. This bit is set when the corresponding bit in CHER is written to one.
PAGE 854
ATSAM4L8/L4/L2 31.8.2 Name: Channel Enable Register CHER Access Type: Write-only Offset: 0x004 Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CHE 23 22 21 20 CHE 15 14 13 12 CHE 7 6 5 4 CHE • CHE: Channel Enable Writing a zero to this bit has no effect. Writing a one to this bit will set the corresponding bit in CHSR.
PAGE 855
ATSAM4L8/L4/L2 31.8.3 Name: Channel Disable Register CHDR Access Type: Write-only Offset: 0x008 Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CHD 23 22 21 20 CHD 15 14 13 12 CHD 7 6 5 4 CHD • CHD: Channel Disable Writing a zero to this bit has no effect. Writing a one to this bit will clear the corresponding bit in CHSR.
PAGE 856
ATSAM4L8/L4/L2 31.8.4 Name: Software Event Register SEV Access Type: Write-only Offset: 0x010 Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SEV 23 22 21 20 SEV 15 14 13 12 SEV 7 6 5 4 SEV • SEV: Software Event Writing a zero to this bit has no effect. Writing a one to this bit will trigger a Software Event for the corresponding channel.
PAGE 857
ATSAM4L8/L4/L2 31.8.5 Name: Channel / User Busy BUSY Access Type: Read-only Offset: 0x014 Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 BUSY 23 22 21 20 BUSY 15 14 13 12 BUSY 7 6 5 4 BUSY • BUSY: Channel Status 0: The corresponding channel and user are idle. 1: The corresponding channel and user are busy.
PAGE 858
ATSAM4L8/L4/L2 31.8.6 Name: Trigger Interrupt Enable Register TRIER Access Type: Write-only Offset: 0x020 Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TRIE 23 22 21 20 TRIE 15 14 13 12 TRIE 7 6 5 4 TRIE • TRIE: Trigger Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will set the corresponding bit in TRIMR.
PAGE 859
ATSAM4L8/L4/L2 31.8.7 Name: Trigger Interrupt Disable Register TRIDR Access Type: Write-only Offset: 0x024 Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TRID 23 22 21 20 TRID 15 14 13 12 TRID 7 6 5 4 TRID • TRID: Trigger Interrupt Disable Writing a zero to this bit has no effect. Writing a one to this bit will clear the corresponding bit in IMR.
PAGE 860
ATSAM4L8/L4/L2 31.8.8 Name: Trigger Interrupt Mask Register TRIMR Access Type: Read-only Offset: 0x028 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TRIM 23 22 21 20 TRIM 15 14 13 12 TRIM 7 6 5 4 TRIM • TRIM: Trigger Interrupt Mask 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. This bit is cleared when the corresponding bit in TRIDR is written to one.
PAGE 861
ATSAM4L8/L4/L2 31.8.9 Name: Trigger Status Register TRSR Access Type: Read-only Offset: 0x030 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TRS 23 22 21 20 TRS 15 14 13 12 TRS 7 6 5 4 TRS • TRS: Trigger Interrupt Status 0: An interrupt event has not occurred 1: An interrupt event has occurred This bit is cleared by writing a one to the corresponding bit in TRSCR.
PAGE 862
ATSAM4L8/L4/L2 31.8.10 Name: Trigger Status Clear Register TRSCR Access Type: Write-only Offset: 0x034 Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TRSC 23 22 21 20 TRSC 15 14 13 12 TRSC 7 6 5 4 TRSC • TRSC: Trigger Interrupt Status Clear Writing a zero to this bit has no effect. Writing a one to this bit will clear the corresponding bit in TRSR.
PAGE 863
ATSAM4L8/L4/L2 31.8.11 Name: Overrun Interrupt Enable Register OVIER Access Type: Write-only Offset: 0x040 Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 OVIE 23 22 21 20 OVIE 15 14 13 12 OVIE 7 6 5 4 OVIE • OVIE: Overrun Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will set the corresponding bit in OVIMR.
PAGE 864
ATSAM4L8/L4/L2 31.8.12 Name: Overrun Interrupt Disable Register OVIDR Access Type: Write-only Offset: 0x044 Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 OVID 23 22 21 20 OVID 15 14 13 12 OVID 7 6 5 4 OVID • OVID: Overrun Interrupt Disable Writing a zero to this bit has no effect. Writing a one to this bit will clear the corresponding bit in IMR.
PAGE 865
ATSAM4L8/L4/L2 31.8.13 Name: Overrun Interrupt Mask Register OVIMR Access Type: Read-only Offset: 0x048 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 OVIM 23 22 21 20 OVIM 15 14 13 12 OVIM 7 6 5 4 OVIM • OVIM: Overrun Interrupt Mask 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. This bit is cleared when the corresponding bit in OVIDR is written to one.
PAGE 866
ATSAM4L8/L4/L2 31.8.14 Name: Overrun Status Register OVSR Access Type: Read-only Offset: 0x050 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 OVS 23 22 21 20 OVS 15 14 13 12 OVS 7 6 5 4 OVS • OVS: Overrun Interrupt Status 0: An interrupt event has not occurred 1: An interrupt event has occurred This bit is cleared by writing a one to the corresponding bit in OVSCR.
PAGE 867
ATSAM4L8/L4/L2 31.8.15 Name: Overrun Status Clear Register OVSCR Access Type: Write-only Offset: 0x054 Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 OVSC 23 22 21 20 OVSC 15 14 13 12 OVSC 7 6 5 4 OVSC • OVSC: Overrun Interrupt Status Clear Writing a zero to this bit has no effect. Writing a one to this bit will clear the corresponding bit in OVSR.
PAGE 868
ATSAM4L8/L4/L2 31.8.16 Name: Channel Multiplexer Register CHMXi Access Type: Read/Write Offset: 0x100 + i*0x004 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - SMX 7 6 5 4 3 2 1 0 - - EVMX • SMX: Software Event Multiplexer 0: The Software Event is not selected. Event / generator is selected by EVMX. 1: The Software Event is selected.
PAGE 869
ATSAM4L8/L4/L2 31.8.17 Name: Event Shaper Register EVSj Access Type: Read/Write Offset: 0x200 + j*0x004 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - IGFON IGFF IGFR 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - EN • IGFON: Input Glitch Filter Status 0: Input Glitch Filter is off. 1: Input Glitch Filter is on. Only present when IGF is used.
PAGE 870
ATSAM4L8/L4/L2 31.8.18 Name: Input Glitch Filter Divider Register IGFDR Access Type: Read/Write Offset: 0x300 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - IGFDR • IGFDR: Input Glitch Filter Divider Selects prescaler division ratio for the system RC clock used for glitch filtering.
PAGE 871
ATSAM4L8/L4/L2 31.8.19 Name: Parameter Register PARAMETER Access Type: Read-only Offset: 0x3F8 Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TRIGOUT 23 22 21 20 EVIN 15 14 13 12 EVS_COUNT 7 6 5 4 IGF_COUNT • TRIGOUT: Number of Trigger Outputs / Channels / Users Number of trigger outputs / channels implemented. No functionality associated. • EVIN: Number of Event Inputs / Generators Number of event inputs. No functionality associated.
PAGE 872
ATSAM4L8/L4/L2 31.8.20 Name: Version Register VERSION Access Type: Read-only Offset: 0x3FC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant Number Variant number of the module. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
PAGE 873
ATSAM4L8/L4/L2 31.9 Module Configuration The specific configuration for each PEVC instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Refer to Section 10. ”Power Manager (PM)” on page 108 for details. Table 31-5. Module Clock Name Module name Clock name PEVC CLK_PEVC The module Register Reset Values are listed below. Table 31-6.
PAGE 874
ATSAM4L8/L4/L2 Table 31-7. Generators CHMXn.
PAGE 875
ATSAM4L8/L4/L2 875 42023E–SAM–07/2013
PAGE 876
ATSAM4L8/L4/L2 32. Audio Bit Stream DAC (ABDACB) Rev: 1.0.0.0 32.1 Features • 16 bit digital stereo DAC • Oversampling D/A conversion architecture • • • • • • • 32.
PAGE 877
ATSAM4L8/L4/L2 32.4 I/O Lines Description Table 32-1. 32.5 I/O Lines Description Pin Name Pin Description Type DAC[0] Output for channel 0 Output DACN[0] Inverted output for channel 0 Output DAC[1] Output for channel 1 Output DACN[1] Inverted output for channel 1 Output CLK Clock output for DAC Output Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 32.5.
PAGE 878
ATSAM4L8/L4/L2 32.6 Functional Description 32.6.1 Construction The Audio Bitstream DAC is divided into several parts, the user interface, the signal processing blocks, and the Sigma Delta modulator blocks. See Figure 32-1 on page 876. The user interface is used to configure the signal processing blocks and to input new data samples to the converter.The signal processing blocks manages volume control, offset control, and upsampling. The Sigma Delta blocks converts the parallel data to1-bit bitstreams.
PAGE 879
ATSAM4L8/L4/L2 32.6.3 Basic operation To convert audio data to a digital bitstream the user must first initialize the ABDACB as described in Section 32.6.2. When the ABDACB is initialized and enabled it will indicate that it is ready to receive new data by setting the Transmit Ready bit in the Status Register (SR.TXRDY). When the TXRDY bit is set in the Status Register the user has to write new samples to Sample Data Register 0 (SDR0) and Sample Data Register 1 (SDR1).
PAGE 880
ATSAM4L8/L4/L2 Figure 32-2. Output signals with CMOC=0 Figure 32-3. Output signals with CMOC=1 32.6.7 Volume Control The Audio Bitstream DAC have two volume control registers, Volume Control Register 0 (VCR0) and Volume Control Register 1 (VCR1), that can be used to adjust the volume for the corresponding channel. The volume control is linear and will only scale each sample according to the value in the Volume Control (VOLUME) field in the volume control registers.
PAGE 881
ATSAM4L8/L4/L2 put of the DAC pins will have a voltage given by the following equation, given that it is configured to run at the default upsampling ratio of 128: 33- ⋅ SDR -------------------------⎞ ⋅ V VDDIO ------------ ⋅ VOLUME V OUT = ⎛ 1 --- – --------15 15 ⎝ 2 128 ⎠ 2 2 –1 If one want to get coherence between the sign of the input data and the output voltage one can use the DATAN outputs or invert the sign of the input data by software. 32.6.
PAGE 882
ATSAM4L8/L4/L2 SDR1) before 1/FS second, or an underrun will occur, as indicated by the Underrun Interrupt bit in SR (SR.TXUR). The interrupt bits in SR are cleared by writing a one to the corresponding bit in the Status Clear Register (SCR). 32.6.12 Frequency Response Figure Figure 32-4 to Figure 32-7 show the frequency response for the system. The sampling frequency used is 48 kHz, but the response will be the same for other sampling frequencies, always having the first zero at FS. Figure 32-4.
PAGE 883
ATSAM4L8/L4/L2 Figure 32-5. Frequency Response up to Sampling Frequency Figure 32-6.
PAGE 884
ATSAM4L8/L4/L2 Figure 32-7.
PAGE 885
ATSAM4L8/L4/L2 32.7 User Interface Table 32-2.
PAGE 886
ATSAM4L8/L4/L2 32.7.1 Name: Control Register CR Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 31 - 30 - 29 - 28 - 27 23 - 22 - 21 - 20 - 19 - 15 - 14 - 13 - 12 - 7 SWRST 6 - 5 MONO 4 CMOC 26 25 24 18 17 DATAFORMAT 16 11 - 10 - 9 - 8 - 3 ALTUPR 2 - 1 SWAP 0 EN FS • FS: Sampling Frequency Must be set to the matching data sampling frequency, see Table 32-3. Table 32-3. Generic Clock Requirements CR.FS Description GCLK (CR.ALTUPR=1) GCLK (CR.
PAGE 887
ATSAM4L8/L4/L2 • DATAFORMAT: Data Word Format Table 32-4. Data Word Format DATAFORMAT Word length 0 32 bits 1 24 bits 2 20 bits 3 18 bits 4 16 bits 5 16 bits compact stereo 6 8 bits 7 8 bits compact stereo Comment Channel 1 sample in bits 31 through 16, channel 0 sample in bits 15 through 0 in SDR0 Channel 1 sample in bits 15 through 8, channel 0 sample in bits 7through 0 in SDR0 • SWRST: Software Reset Writing a zero to this bit does not have any effect.
PAGE 888
ATSAM4L8/L4/L2 32.7.2 Name: Sample Data Register 0 SDR0 Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DATA[31:24] 23 22 21 20 DATA[23:16] 15 14 13 12 DATA[15:8] 7 6 5 4 DATA[7:0] • DATA: Sample Data Sample Data for channel 0 in two’s complement format. Data must be right-justified, see Table 32-5. Table 32-5.
PAGE 889
ATSAM4L8/L4/L2 32.7.3 Name: Sample Data Register 1 SDR1 Access Type: Read/Write Offset: 0x08 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DATA[31:24] 23 22 21 20 DATA[23:16] 15 14 13 12 DATA[15:8] 7 6 5 4 DATA[7:0] • DATA: Sample Data Sample Data for channel 1 in two’s complement format. Data must be right-justified, see Table 32-5 on page 888.
PAGE 890
ATSAM4L8/L4/L2 32.7.4 Name: Volume Control Register 0 VCR0 Access Type: Read/Write Offset: 0x0C Reset Value: 0x00000000 31 MUTE 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 13 12 11 VOLUME[14:8] 10 9 8 7 6 5 4 3 2 1 0 VOLUME[7:0] • MUTE: Mute 0: Channel 0 is not muted. 1: Channel 0 is muted. • VOLUME: Volume Control 15-bit value adjusting the volume for channel 0.
PAGE 891
ATSAM4L8/L4/L2 32.7.5 Name: Volume Control Register 1 VCR1 Access Type: Read/Write Offset: 0x10 Reset Value: 0x00000000 31 MUTE 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 13 12 11 VOLUME[14:8] 10 9 8 7 6 5 4 3 2 1 0 VOLUME[7:0] • MUTE: Mute 0: Channel 1 is not muted. 1: Channel 1 is muted. • VOLUME: Volume Control 15-bit value adjusting the volume for channel 1.
PAGE 892
ATSAM4L8/L4/L2 32.7.6 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x14 Reset Value: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 TXUR 1 TXRDY 0 - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
PAGE 893
ATSAM4L8/L4/L2 32.7.7 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x18 Reset Value: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 TXUR 1 TXRDY 0 - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
PAGE 894
ATSAM4L8/L4/L2 32.7.8 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x1C Reset Value: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 TXUR 1 TXRDY 0 - 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one.
PAGE 895
ATSAM4L8/L4/L2 32.7.9 Name: Status Register SR Access Type: Read-only Offset: 0x20 Reset Value: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 TXUR 1 TXRDY 0 BUSY • TXUR: Transmit Underrun This bit is cleared when no underrun has occurred since the last time this bit was cleared (by reset or by writing to SCR).
PAGE 896
ATSAM4L8/L4/L2 32.7.10 Name: Status Clear Register SCR Access Type: Write-only Offset: 0x24 Reset Value: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 TXUR 1 TXRDY 0 - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in SR and the corresponding interrupt request.
PAGE 897
ATSAM4L8/L4/L2 32.7.11 Name: Parameter Register PARAMETER Access Type: Read-only Offset: 0x28 Reset Value: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - Reserved. No functionality associated.
PAGE 898
ATSAM4L8/L4/L2 32.7.12 Name: Version Register VERSION Access Type: Read-only Offset: 0x2C Reset Value: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 18 17 16 15 - 14 - 13 - 12 - 11 10 9 VERSION[11:8] 8 7 6 5 4 3 2 0 VARIANT 1 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
PAGE 899
ATSAM4L8/L4/L2 32.8 Module Configuration The specific configuration for each ABDACB instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Refer to Section 10. ”Power Manager (PM)” on page 108 for details. Table 32-6. ABDACB Clocks Clock Name Description CLK_ABDACB Clock for the ABDACB bus interface GCLK The generic clock used for the ABDACB is GCLK6 Table 32-7.
PAGE 900
ATSAM4L8/L4/L2 33. Digital to Analog Converter Controller (DACC) Rev. 1.1.1.0 33.1 Features • 10-bit Resolution • Hardware Trigger – External Trigger Pins – Peripheral Event • PDCA Support • DACC Timings Configuration • Internal FIFO for flexibility and efficiency 33.2 Overview The Digital-to-Analog Converter Controller (DACC) supports 10-bit resolution. Data to be converted are sent in a common register. External triggers, through ext_trig pins, and internal triggers (events) are configurable.
PAGE 901
ATSAM4L8/L4/L2 33.3 Block Diagram Figure 33-1. Digital-to-Analog Converter Controller Block Diagram DAC Controller EXT_TRIG Peripheral event Trigger Selection Control Logic Interrupt Controller Analog cell PDCA Sample & Hold DAC Core User Interface APB VOUT 33.4 Signal Description Table 33-1. DACC Pin Description Pin Name Description VOUT Analog output EXT_TRIG External trigger 33.5 33.5.
PAGE 902
ATSAM4L8/L4/L2 33.5.2 33.6 33.6.1 Interrupt Sources The DACC interrupt line is connected on one of the internal sources of the NVIC. Using the DACC interrupt requires the NVIC to be programmed first. Functional Description Digital-to-Analog Conversion DACC uses the APB clock (CLK_DACC) to perform conversions. DAC is enabled by writing a one to DACEN in Mode Register (MR). Once enabled, DAC is ready to operate after a startup time (see electrical characteristics).
PAGE 903
ATSAM4L8/L4/L2 Figure 33-2. Internal Trigger Figure 33-3. External Trigger 33.6.4 Write Protection Registers In order to provide security to the DACC, a write protection mode is implemented. This mode is enabled by writing a one in Write Protect Enable (WPE) in the Write Protect Mode Register (WPMR) and disabled by writing a zero. Writing to WPMR requires to write a security key in Write Protect Key (WPMR.WPKEY). The value is “DAC” in ASCII, corresponding to 0x444143.
PAGE 904
ATSAM4L8/L4/L2 33.7 User Interface Table 33-2.
PAGE 905
ATSAM4L8/L4/L2 33.7.1 Name: Control Register CR Access Type: Write-only Offset: 0x00 Reset Value: - 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 SWRST • SWRST: Software Reset Writing a one to this bit resets the DACC. Writing a zero to this bit has no effect.
PAGE 906
ATSAM4L8/L4/L2 33.7.2 Name: Mode Register MR Access: Read/Write Offset: 0x04 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 TRGSEL 1 0 TRGEN CLKDIV 23 22 21 20 CLKDIV 15 14 13 12 STARTUP 7 – 6 – 5 WORD 4 DACEN This register can only be written if the WPEN bit is cleared in Write Protect Mode Register. • CLKDIV: Clock Divider for Internal Trigger Trigger period is CLKDIV * APB clock period.
PAGE 907
ATSAM4L8/L4/L2 33.7.3 Name: Conversion Data Register CDR Access: Write-only Offset: 0x08 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DATA 23 22 21 20 DATA 15 14 13 12 DATA 7 6 5 4 DATA • DATA: Data to Convert When the MR.WORD is zero, only DATA[15:0] is used for conversion else DATA[31:0] is used to write 2 data for conversion.
PAGE 908
ATSAM4L8/L4/L2 33.7.4 Name: Interrupt Enable Register IER Access: Write-only Offset: 0x0C Reset Value: - 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 TXRDY Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
PAGE 909
ATSAM4L8/L4/L2 33.7.5 Name: Interrupt Disable Register IDR Access: Write-only Offset: 0x10 Reset Value: - 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 TXRDY Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
PAGE 910
ATSAM4L8/L4/L2 33.7.6 Name: Interrupt Mask Register IMR Access: Read-only Offset: 0x14 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 TXRDY 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one.
PAGE 911
ATSAM4L8/L4/L2 33.7.7 Name: Interrupt Status Register ISR Access: Read-only Offset: 0x18 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 TXRDY • TXRDY: Transmit Ready 0 = DACC is not ready to accept new conversion requests. 1 = DACC is ready to accept new conversion requests.
PAGE 912
ATSAM4L8/L4/L2 33.7.8 Name: Write Protect Mode Register WPMR Access: Read/Write Offset: 0xE4 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 – 6 – 5 – 4 – • WPKEY: Write Protect KEY This security code is needed to set/reset the WPEN bit. Must be filled with “DAC” ASCII code (0x444143). • WPEN: Write Protect Enable 0 = Disables the Write Protect. 1 = Enables the Write Protect.
PAGE 913
ATSAM4L8/L4/L2 33.7.9 Name: Write Protect Status Register WPSR Access: Read-only Offset: 0xE8 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 – 2 – 1 – 0 WPROTERR WPROTADDR 7 – 6 – 5 – 4 – • WPROTADDR: Write Protection Error Address Address of the register write request which generated the error. • WPROTERR: Write Protection Error 0: no error. 1: write protection error.
PAGE 914
ATSAM4L8/L4/L2 33.7.10 Name: Version Register VERSION Access: Read-only Offset: 0xFC Reset Value: - 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 17 VARIANT 16 15 – 14 – 13 – 12 – 11 10 9 8 7 6 5 4 3 1 0 VERSION 2 VERSION • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Reserved. No functionality associated.
PAGE 915
ATSAM4L8/L4/L2 33.8 Module Configuration The specific configuration for each DACC instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Refer to Section 10. ”Power Manager (PM)” on page 108 for details. Table 33-3. ABDACB Clocks Clock Name Description CLK_DACC Clock for the DACC bus interface Table 33-4.
PAGE 916
ATSAM4L8/L4/L2 34. Capacitive Touch Module (CATB) Rev: 1.0.0.0 34.
PAGE 917
ATSAM4L8/L4/L2 34.3 Block Diagram Figure 34-1. CATB Block Diagram SENSE0 . . . RC oscillator GCLK CLK_ACQ CKSEL SENSEn PINSEL Capacitance Counter Filter DIS TOP SPREAD REPEAT CHARGET Threshold INTERRUPT LEVEL TIDLE IDLE TLEVEL RAW THRESH LENGTH Interface Registers CLK_CATB 34.4 DMA Control I/O Lines Description Table 34-1. 34.
PAGE 918
ATSAM4L8/L4/L2 The CATB also depends on the acquisition clock (CLK_ACQ). This clock can be configured to be either a dedicated generic clock (GCLK), or a dedicated RC oscillator. The GCLK must be enabled in the System Control Interface (SCIF) before the CATB can be used. The RC oscillator is automatically enabled when needed. The RC oscillator and GCLK used is specified in the Module Configuration section. 34.5.4 Interrupts The CATB interrupt request line is connected to the NVIC.
PAGE 919
ATSAM4L8/L4/L2 Capacitive changes can correspond to touch, proximity, out-of-touch, or events such as change of power supply (ripple or ground shift). Fast changing environmental parameters can also affect the touch measurements. While the CATB can only measure and hold configuration and state for one sensor at the time, the Peripheral DMA Controller can be used with a buffer in RAM to rotate sensor configuration for the CATB. 20 bytes of RAM are then needed per sensor. Figure 34-3.
PAGE 920
ATSAM4L8/L4/L2 average over. They should equal 2 -----------------------------------------------T ⋅ sample rate + 1 with typical T values being 5s for TIMING.TIDLE, and 0.1s for TIMING.TLEVEL. Because the Idle Tracker is used to bias the measured values around zero, IDLE needs to be initialized with an appropriate value in order to avoid saturation of the filter. This value can either be obtained experimentally and stored in the application, or by writing a one to the Initialize Idle bit (CR.
PAGE 921
ATSAM4L8/L4/L2 (THRESH.RTHRESH), and a fractional part (THRESH.FTHRESH). The user should select a threshold value that corresponds to application typical sensor signal strengths. The threshold values are compared to the LEVEL register values, and the In Touch bit in the Interrupt Status Register (ISR.INTCH) is set when the value in the LEVEL register is larger than the value in the THRESH register, while the Out of Touch bit (ISR.
PAGE 922
ATSAM4L8/L4/L2 The RAW n and RAW n – 1 values can be observed in the RAWA and RAWB fields respectively in the RAW register. These values can be logged, and the user can simulate the rest of the filter for tuning and debugging purposes. The Idle tracker must be set up using TIMING.TIDLE to function as a slow-moving average to be subtracted from the measured values to remove the constant bias. This biases the signal around zero, with fast changes in capacitance shown as deviations from zero.
PAGE 923
ATSAM4L8/L4/L2 4. The updated data is written back to memory, overwriting the previous configuration and state 5. The DMA write pointer is incremented, and the next write to memory will write the data for sensor 2 Using the ring buffer feature of the DMA controller, the system will go cyclically through the sensors set up in memory. Detected touch events for different sensor configurations are reported in the In-touch Status bits in the In-Touch Registers (INTCHn.
PAGE 924
ATSAM4L8/L4/L2 • LENGTH_COUNT: Number of samples over threshold – This value is used to track how many samples that have crossed the threshold (THRESH.RTHRESH and THRESH.FTHRESH), and is compared to THRESH.LENGTH. This field should be initialized to zero. • THRESH.LENGTH: Threshold length • THRESH.DIR: Threshold direction • THRESH.RTHRESH: Threshold, integer part • THRESH.FTHRESH: Threshold, fractional part – Refer to corresponding fields in Section 34.7.7 ”Threshold Register” on page 935. • IDLE.
PAGE 925
ATSAM4L8/L4/L2 3. Configure common setup for all sensors (such as CNTCR.TOP, CNTCR.CHARGET, CNTCR.SPREAD). 4. Write a one to the DMA Enable (CR.DMAEN) and the CR.RUN bit. Having a separate STATUSSEL and PINSEL allows the user to set up e.g. multiple thresholds on the same pin. This can be used for having multi-level threshold (proximity and touch), or for having different signs for the threshold, to capture both decrease and increase in capacitance on the same sensor. 34.6.
PAGE 926
ATSAM4L8/L4/L2 ger one acquisition per event. The peripheral-event-triggered operation is enabled by writing a one to the Event Triggered Operation bit in the Control Register (CR.ETRIG). In this mode, the CATB will start the required clocks for performing an acquisition, and can thereby operate in all sleep modes where the peripheral event generator is running.
PAGE 927
ATSAM4L8/L4/L2 34.7 User Interface Table 34-3.
PAGE 928
ATSAM4L8/L4/L2 34.7.1 Name: Control Register CR Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 SWRST - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 10 9 8 - CHARGET 11 ESAMPLES 7 6 5 4 3 2 1 0 DMAEN DIFF CKSEL INTRES ETRIG IIDLE RUN EN • SWRST: Software Reset Writing a zero to this bit has no effect. Writing a one to this bit resets the CATB. The CATB will be disabled after the reset.
PAGE 929
ATSAM4L8/L4/L2 • ETRIG: Event Triggered Operation 0: Normal continuous acquisition mode of operation. 1: CATB acquisitions are triggered by the Peripheral Event System. • IIDLE: Initialize Idle Value 0: The IDLE register will only be updated by the CATB, or if written to. 1: The IDLE register is set to the next measured value. This bit always reads as zero. • RUN: Start Operation Writing a zero to this bit will stop the CATB. Writing a one to this bit will usually start acquisitions immediately. If CR.
PAGE 930
ATSAM4L8/L4/L2 34.7.2 Name: Counter Control Register CNTCR Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 31 30 - 29 28 27 26 REPEAT 23 22 21 25 24 SPREAD 20 19 18 17 16 11 10 9 8 3 2 1 0 TOP[23:16] 15 14 13 12 TOP[15:8] 7 6 5 4 TOP[7:0] Note: This register must not be written to during CATB operation (CR.RUN is one). • REPEAT: Repeat Measurements Measurements are repeated REPEAT+1 times in the acqusition block.
PAGE 931
ATSAM4L8/L4/L2 34.7.3 Name: Sensor Idle Level IDLE Access Type: Read/Write Offset: 0x08 Reset Value: 0x00000000 31 30 29 28 - - - - 23 22 21 20 27 26 25 24 RIDLE[15:12] 19 18 17 16 11 10 9 8 1 0 RIDLE[11:4] 15 14 13 12 RIDLE[3:0] 7 6 FIDLE[11:8] 5 4 3 2 FIDLE[7:0] This register value is subtracted from initial measurement data in order to determine the relative capacitance.
PAGE 932
ATSAM4L8/L4/L2 34.7.4 Name: Sensor Relative Level LEVEL Access Type: Read-only Offset: 0x0C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 1 0 RLEVEL[7:4] 11 10 RLEVEL[3:0] 7 6 FLEVEL[11:8] 5 4 3 2 FLEVEL[7:0] This register contains the latest sensor measurement value. It has been filtered, subtracted from the IDLE register values, and smoothened.
PAGE 933
ATSAM4L8/L4/L2 34.7.5 Name: Sensor Raw Value RAW Access Type: Read-only Offset: 0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 RAWB 23 22 21 20 RAWA 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 • RAWB: Last Sensor Raw Value The unfiltered counter value from last acquisition. • RAWA: Current Sensor Raw Value The unfiltered counter value from last acquisition, with IDLE subtracted.
PAGE 934
ATSAM4L8/L4/L2 34.7.6 Name: Filter Timing Register TIMING Access Type: Read/Write Offset: 0x14 Reset Value: 0x00000000 31 30 29 28 - - - - 23 22 21 20 27 26 25 24 TIDLE[11:8] 19 18 17 16 11 10 9 8 1 0 TIDLE[7:0] 15 14 13 12 - - - - 7 6 5 4 TLEVEL[11:8] 3 2 TLEVEL[7:0] • TIDLE: Idle Smoothening This field determines how fast Idle tracker should track the measured samples. Note that some of the LSB’s of this field might not be implemented.
PAGE 935
ATSAM4L8/L4/L2 34.7.7 Name: Threshold Register THRESH Access Type: Read/Write Offset: 0x18 Reset Value: 0x00000000 31 30 29 28 - - - 23 22 21 20 DIR - - - 15 14 13 12 27 6 25 24 17 16 LENGTH 19 18 RTHRESH[7:4] 11 RTHRESH[3:0] 7 26 10 9 8 FTHRESH[11:8] 5 4 3 2 1 0 FTHRESH[7:0] • LENGTH: Threshold Length The amount of successive samples that have to be beyond the threshold before a in- or out-of-touch event is detected.
PAGE 936
ATSAM4L8/L4/L2 34.7.8 Name: Pin Selection Register PINSEL Access Type: Read/Write Offset: 0x1C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 PINSEL The number of available bits in this register is device dependent. Refer to the Module Configuration section for details. • PINSEL: Pin Select The pin selected for touch acquisition.
PAGE 937
ATSAM4L8/L4/L2 34.7.9 Name: Direct Memory Access Register DMA Access Type: Read/Write Offset: 0x20 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DMA[31:24] 23 22 21 20 DMA[23:16] 15 14 13 12 DMA[15:8] 7 6 5 4 DMA[7:0] Note: This register is used for DMA transfers between the CATB and RAM. This register must not be read or written by the user.
PAGE 938
ATSAM4L8/L4/L2 34.7.10 Name: Interrupt Status Register ISR Access Type: Read-only Offset: 0x24 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - OUTTCH INTCH SAMPLE Bits in this register are cleared by writing a one to the corresponding bit in the Status Clear Register (SCR).
PAGE 939
ATSAM4L8/L4/L2 34.7.11 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x28 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - OUTTCH INTCH SAMPLE Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
PAGE 940
ATSAM4L8/L4/L2 34.7.12 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x2C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - OUTTCH INTCH SAMPLE Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
PAGE 941
ATSAM4L8/L4/L2 34.7.13 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x30 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - OUTTCH INTCH SAMPLE 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
PAGE 942
ATSAM4L8/L4/L2 34.7.14 Name: Status Clear Register SCR Access Type: Write-only Offset: 0x34 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - OUTTCH INTCH SAMPLE Writing a zero to a bit in this register has no effect.
PAGE 943
ATSAM4L8/L4/L2 34.7.
PAGE 944
ATSAM4L8/L4/L2 34.7.
PAGE 945
ATSAM4L8/L4/L2 34.7.
PAGE 946
ATSAM4L8/L4/L2 34.7.
PAGE 947
ATSAM4L8/L4/L2 34.7.19 Name: Parameter Register PARAMETER Access Type: Read-only Offset: 0xF8 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 FRACTIONAL 11 10 9 8 3 2 1 0 NSTATUS 7 6 5 4 NPINS • FRACTIONAL: Number of Fractional bits The number of implemented fractional bits. • NSTATUS: Number of Status bits The number of implemented status bits. • NPINS: Number of Pins The number of connected pins.
PAGE 948
ATSAM4L8/L4/L2 34.7.20 Name: Version Register VERSION Access Type: Read-only Offset: 0xFC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
PAGE 949
ATSAM4L8/L4/L2 34.8 Module Configuration The specific configuration for each CATB instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Refer to Section 10. ”Power Manager (PM)” on page 108 for details. Table 34-4. CATB Configuration Feature CATB Number of sensors/connected pins 32 Number of status bits in STATUSSEL 32 Number of fractional bits implemented in IDLE, LEVEL, TIMING, and THRESH.
PAGE 950
ATSAM4L8/L4/L2 35. True Random Number Generator (TRNG) Rev: 1.0.3.0 35.1 Features • Passed NIST Special Publication 800-22 Tests Suite • Passed Diehard Random Tests Suite • Provides a 32-bit Random Number Every 84 Clock Cycles 35.2 Overview The True Random Number Generator provides 32-bit random numbers. 35.3 Functional Description The True Random Number Generator (TRNG) passes the American NIST Special Publication 800-22 and Diehard Random Tests Suites.
PAGE 951
ATSAM4L8/L4/L2 35.4 User Interface Table 35-1. TRNG Register Memory Map Offset Notes: Register Name Access Reset 0x00 Control Register CR Write-only – 0x10 Interrupt Enable Register IER Write-only – 0x14 Interrupt Disable Register IDR Write-only – 0x18 Interrupt Mask Register IMR Read-only 0x0000_0000 0x1C Interrupt Status Register ISR Read-only 0x0000_0000 0x50 Output Data Register ODATA Read-only 0x0000_0000 0xFC Version Register VERSION Read-only –(1) 1.
PAGE 952
ATSAM4L8/L4/L2 35.4.1 Name: Control Register CR Access Type: Write-only Offset: 0x00 Reset Value: – 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 KEY 23 22 21 20 KEY 15 14 13 12 KEY 7 6 5 4 3 2 1 0 – – – – – – – ENABLE • KEY: Security Key KEY = 0x524e47 (RNG in ASCII) This field must be written to 0x524E47 for a write operation to be effective. • ENABLE: Enables the TRNG to provide random values Writing a zero to this bit disables the TRNG.
PAGE 953
ATSAM4L8/L4/L2 35.4.2 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x10 Reset Value: – 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – DATRDY Writing a zero to a bit in this register has no effect.
PAGE 954
ATSAM4L8/L4/L2 35.4.3 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x14 Reset Value: – 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – DATRDY Writing a zero to a bit in this register has no effect.
PAGE 955
ATSAM4L8/L4/L2 35.4.4 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x18 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – DATRDY 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. This bit is cleared when the corresponding bit in IDR is written to one.
PAGE 956
ATSAM4L8/L4/L2 35.4.5 Name: Interrupt Status Register ISR Access Type: Read-only Offset: 0x34 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – DATRDY • DATRDY: Data Ready 0 = Output data is not valid or TRNG is disabled. 1 = New Random value is completed. DATRDY is cleared when this register is read.
PAGE 957
ATSAM4L8/L4/L2 35.4.6 Name: Output Data Register ODATA Access Type: Read-only Offset: 0x34 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ODATA 23 22 21 20 ODATA 15 14 13 12 ODATA 7 6 5 4 ODATA • ODATA: Output Data The 32-bit Output Data register contains the 32-bit random data.
PAGE 958
ATSAM4L8/L4/L2 35.4.7 Name: Version Register VERSION Access Type: Read-only Offset: 0xFC Reset Value: - 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – 15 14 13 12 11 – – – – 7 6 5 4 VARIANT 10 9 8 1 0 VERSION 3 2 VERSION • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
PAGE 959
ATSAM4L8/L4/L2 35.5 Module Configuration The specific configuration for each TRNG instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Refer to Section 10. ”Power Manager (PM)” on page 108 for details. Table 35-2. TRNG Clock Name Module Name Clock Name Description TRNG CLK_TRNG Peripheral clock for TRNG Table 35-3.
PAGE 960
ATSAM4L8/L4/L2 36. Glue Logic Controller (GLOC) Rev: 1.0.2.0 36.1 Features • • • • 36.2 Glue logic for general purpose PCB design Programmable lookup table Up to four inputs supported per lookup table Optional filtering of output Overview The Glue Logic Controller (GLOC) contains programmable logic which can be connected to the device pins. This allows the user to eliminate logic gates for simple glue logic functions on the PCB. The GLOC consists of a number of lookup table (LUT) units.
PAGE 961
ATSAM4L8/L4/L2 36.4 I/O Lines Description Table 36-1. I/O Lines Description Pin Name Pin Description Type IN0-INm Inputs to lookup tables Input OUT0-OUTn Output from lookup tables Output Each LUT have 4 inputs and one output. The inputs and outputs for the LUTs are mapped sequentially to the inputs and outputs. This means that LUT0 is connected to IN0 to IN3 and OUT0. LUT1 is connected to IN4 to IN7 and OUT1. In general, LUTn is connected to IN[4n] to IN[4n+3] and OUTn. 36.
PAGE 962
ATSAM4L8/L4/L2 36.6.2 Configuring the Lookup Table The lookup table in each LUT unit can generate any logic expression OUT as a function of up to four inputs, IN[3:0]. The truth table for the expression is written to the TRUTH register for the LUT. Table 36-2 shows the truth table for LUT0. The truth table for LUTn is written to TRUTHn, and the corresponding input and outputs will be IN[4n] to IN[4n+3] and OUTn. Table 36-2. 36.6.
PAGE 963
ATSAM4L8/L4/L2 36.7 User Interface Table 36-3. GLOC Register Memory Map Offset Register Register Name Access Reset 0x00+n*0x08 Control Register n CRn Read/Write 0x00000000 0x04+n*0x08 Truth Table Register n TRUTHn Read/Write 0x00000000 0x38 Parameter Register PARAMETER Read-only - (1) 0x3C Version Register VERSION Read-only - (1) Note: 1. The reset values are device specific. Refer to the Module Configuration section at the end of this chapter.
PAGE 964
ATSAM4L8/L4/L2 36.7.1 Name: Control Register n CRn Access Type: Read/Write Offset: 0x00+n*0x08 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 FILTEN - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - AEN • FILTEN: Filter Enable 1: The output is glitch filtered. 0: The output is not glitch filtered. • AEN: Enable IN Inputs Input IN[n] is enabled when AEN[n] is one.
PAGE 965
ATSAM4L8/L4/L2 36.7.
PAGE 966
ATSAM4L8/L4/L2 36.7.3 Name: Parameter Register PARAMETER Access Type: Read-only Offset: 0x38 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 LUTS • LUTS: Lookup Table Units Implemented This field contains the number of lookup table units implemented in this device.
PAGE 967
ATSAM4L8/L4/L2 36.7.4 Name: Version Register VERSION Access Type: Read-only Offset: 0x3C Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
PAGE 968
ATSAM4L8/L4/L2 36.8 Module Configuration The specific configuration for each GLOC instance is listed in the following tables.The GLOC bus clocks listed here are connected to the system bus clocks. Refer to Section 10. ”Power Manager (PM)” on page 108 for details. Table 36-4. GLOC Configuration Feature GLOC Number of LUT units 2 Table 36-5. GLOC Clocks Clock Name Description CLK_GLOC Clock for the GLOC bus interface GCLK The generic clock used for the GLOC is GCLK5 Table 36-6.
PAGE 969
ATSAM4L8/L4/L2 37. Analog Comparator Interface (ACIFC) Rev: 1.0.0.0 37.
PAGE 970
ATSAM4L8/L4/L2 37.3 Block Diagram Figure 37-1. ACIFC Block Diagram Analog Comparators AC0_FAST ACIFC ACTEST0 Peripheral Bus AC0_HYS ACAP0 CLK_ACIFC INP ACOUT0 + AC0 ACAN0 INN INTERRUPT GENERATION AC0_INSELN ACTEST AC1_FAST IRQ AC1_HYS ACBP0 PERIPHERAL EVENT GENERATION INP + AC1 ACBN0 INN TRIGGER ACOUT1 PERUIPHERAL EVENTS AC1_INSELN ... ACTEST1 37.4 I/O Lines Description Table 37-1.
PAGE 971
ATSAM4L8/L4/L2 Table 37-2. Channel 37.5 Pin Mapping Pins (Normal Mode) 4 ACAP2, ACAN2 5 ACBP2, ACBN2 6 ACAP3, ACAN3 7 ACBP3, ACBN3 Window pair Pins (Window Mode) 2 ACAP2, ACBN2 3 ACAP3, ACBN3 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 37.5.1 I/O Lines The ACIFC pins are multiplexed with other peripherals. The user must first configure the I/O Controller to give control of the pins to the ACIFC. 37.5.
PAGE 972
ATSAM4L8/L4/L2 mode, while others are in window mode. There are restrictions on which ACs can be grouped in a window mode, see Section 37.6.5. 37.6.1 Analog Comparator Operation Each AC can be in one of four measurement modes, determined by CONFx.
PAGE 973
ATSAM4L8/L4/L2 Corresponding peripheral events and interrupts are generated if enabled. No new comparisons will be performed. 37.6.1.4 Selecting Comparator Inputs Each Analog Comparator has one positive (INP) and one negative (INN) input. The positive input is fed from an external input pin (ACAPx, ACBPx). There are several sources for negative input including external input pin ACA/BNx. The Negative Input Select field (CONFx.INSELN) selects the source for the negative input. See CONFx.
PAGE 974
ATSAM4L8/L4/L2 • Startup time interrupt (bit ISR.SUTINTx), each AC can generate an interrupt when the startup time is over. • AC output based interrupt (bit ISR.ACINTx). In normal mode, the following interrupt sources are available: – When VINP > VINN – When VINP < VINN – On toggle of the AC output (ACOUT) – When comparison has been done The user selects the interrupt source by writing to the Interrupt Settings field in the ACx Configuration Register (CONFx.IS). 37.6.4.
PAGE 975
ATSAM4L8/L4/L2 Figure 37-2. Analog Comparator Interface in Window mode ACAPx + ACANx ACx ACOUTx - Interrupt Generator IRQ CONFx.INSELN ACWOUT COMMON Comparator pair Window Module ACOUTx+1 ACx+1 CONFx+1.INSELN 37.6.5.1 SR.ACCSn - ACBNx WINDOW MODE PERIPHERAL EVENT SR.WFCSn + ACBPx Peripheral Event Generator Window Window Mode Output When operating in window mode, each AC generates the same ACOUT outputs as in normal mode, see Section 37.6.4.1.
PAGE 976
ATSAM4L8/L4/L2 • On toggle of the window compare output (ACWOUT). • When the comparison in both ACs in the window mode is ready. • When the common input voltage enters the window (i.e., rising-edge of ACWOUT). • When the common input voltage leaves the window (i.e., falling-edge of ACWOUT). 37.6.5.3 Window Mode Peripheral Events When operating in window mode, each AC can generate the same peripheral events as in normal mode, see Section 37.6.4.3.
PAGE 977
ATSAM4L8/L4/L2 37.6.7 Power Dissipation and Speed Trade-off ACIFC is able to control whether an AC operates in fast or low-power mode, allowing a trade-off between its active power dissipation and speed. The desired mode is selected by writing to the FAST bit in the CONFx register (CONFx.FAST). When CONFx.FAST is zero (default), the corresponding AC operates in low-power mode. When CONFx.FAST is one, it operates in fast mode.
PAGE 978
ATSAM4L8/L4/L2 37.9 User Interface Table 37-4.
PAGE 979
ATSAM4L8/L4/L2 37.9.1 Name: Control Register CTRL Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 ACTEST - ESTART USTART - - EVENTEN EN • ACTEST: Analog Comparator Test Mode 0: The Analog Comparator outputs are connected to the logic in ACIFC.
PAGE 980
ATSAM4L8/L4/L2 37.9.
PAGE 981
ATSAM4L8/L4/L2 37.9.3 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - WFINT3 WFINT2 WFINT1 WFINT0 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 SUTINT7 ACINT7 SUTINT6 ACINT6 SUTINT5 ACINT5 SUTINT4 ACINT4 7 6 5 4 3 2 1 0 SUTINT3 ACINT3 SUTINT2 ACINT2 SUTINT1 ACINT1 SUTINT0 ACINT0 Writing a zero to a bit in this register has no effect.
PAGE 982
ATSAM4L8/L4/L2 37.9.4 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x14 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - WFINT3 WFINT2 WFINT1 WFINT0 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 SUTINT7 ACINT7 SUTINT6 ACINT6 SUTINT5 ACINT5 SUTINT4 ACINT4 7 6 5 4 3 2 1 0 SUTINT3 ACINT3 SUTINT2 ACINT2 SUTINT1 ACINT1 SUTINT0 ACINT0 Writing a zero to a bit in this register has no effect.
PAGE 983
ATSAM4L8/L4/L2 37.9.5 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x18 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - WFINT3 WFINT2 WFINT1 WFINT0 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 SUTINT7 ACINT7 SUTINT6 ACINT6 SUTINT5 ACINT5 SUTINT4 ACINT4 7 6 5 4 3 2 1 0 SUTINT3 ACINT3 SUTINT2 ACINT2 SUTINT1 ACINT1 SUTINT0 ACINT0 0: The corresponding interrupt is disabled.
PAGE 984
ATSAM4L8/L4/L2 37.9.
PAGE 985
ATSAM4L8/L4/L2 37.9.7 Name: Interrupt Status Clear Register ICR Access Type: Write-only Offset: 0x20 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - WFINT3 WFINT2 WFINT1 WFINT0 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 SUTINT7 ACINT7 SUTINT6 ACINT6 SUTINT5 ACINT5 SUTINT4 ACINT4 7 6 5 4 3 2 1 0 SUTINT3 ACINT3 SUTINT2 ACINT2 SUTINT1 ACINT1 SUTINT0 ACINT0 Writing a zero to a bit in this register has no effect.
PAGE 986
ATSAM4L8/L4/L2 37.9.8 Name: Test Register TR Access Type: Read/Write Offset: 0x24 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 ACTEST7 ACTEST6 ACTEST5 ACTEST4 ACTEST3 ACTEST2 ACTEST1 ACTEST0 • ACTESTx: ACx Output Override Value 0: Normal operating mode. 1: If CTRL.ACTEST is one, ACx output is the bit value ACTESTx.
PAGE 987
ATSAM4L8/L4/L2 37.9.9 Name: Parameter Register PARAMETER Access Type: Read-only Offset: 0x30 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - WIMPL3 WIMPL2 WIMPL1 WIMPL0 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 ACIMPL7 ACIMPL6 ACIMPL5 ACIMPL4 ACIMPL3 ACIMPL2 ACIMPL1 ACIMPL0 • WIMPLx: Window x Mode Implemented 0: Window x mode is not implemented. 1: Window x mode is implemented.
PAGE 988
ATSAM4L8/L4/L2 37.9.10 Name: Version Register VERSION Access Type: Read-only Offset: 0x34 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
PAGE 989
ATSAM4L8/L4/L2 37.9.11 Name: Windowx Configuration Register CONFWx Access Type: Read/Write Offset: 0x80,0x84,0x88,0x8C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - WFEN 15 14 13 12 11 10 9 8 - - - - WEVEN 7 6 5 4 3 - - - - - WEVSRC 2 1 0 WIS • WFEN: Window Mode Enable 0: Window mode is disabled. 1: Window mode is enabled.
PAGE 990
ATSAM4L8/L4/L2 • WEVSRC: Peripheral Event Source Selection for Window Mode WEVSRC Peripheral Source Selection 0 0 0 ACWOUT rising edge 0 0 1 ACWOUT falling edge 0 1 0 ACWOUT rising or falling edge 0 1 1 Inside window 1 0 0 Outside window 1 0 1 Measure done 1 1 0 Reserved 1 1 1 Reserved • WIS: Window Mode Interrupt Settings WIS Interrupt Settings 0 0 0 Window interrupt as soon as the common input voltage is inside the window 0 0 1 Window interrupt as soon as the com
PAGE 991
ATSAM4L8/L4/L2 37.9.
PAGE 992
ATSAM4L8/L4/L2 • MODE: Analog Comparator Mode MODE Mode selected 0 0 Off 0 1 Continuous measurement mode 1 0 User triggered single measurement mode 1 1 Peripheral event triggered single measurement mode • IS: Interrupt Settings IS Interrpt setting 0 0 When VINP > VINN 0 1 When VINP < VINN 1 0 On toggle of ACOUT 1 1 When comparison of VINP and VINN is done 992 42023E–SAM–07/2013
PAGE 993
ATSAM4L8/L4/L2 37.10 Module configuration The specific configuration for each ACIFC instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Refer to the Power Manager chapter for details. Table 37-5. ACIFC Configuration Feature ACIFC AC_NO 8 ACW_NO 4 Table 37-6. ACIFC Clocks Clock Name Description CLK_ACIFC Clock for the ACIFC bus interface Table 37-7. INSELN CONFx.
PAGE 994
ATSAM4L8/L4/L2 38. ADC Interface (ADCIFE) Rev. 1.0.0.0 38.1 Features • • • • • • • • • • 38.
PAGE 995
ATSAM4L8/L4/L2 38.3 Block diagram Figure 38-1. ADCIFE Block Diagram A D C IF E T im e r T rig g e r/P E V C S o u rc e s T rig g e r S e le c tio n S equencer C L K _ A D C IF E ADVREFP G C LK GNDREF R e fe re n c e B u ffe r Bandgap D M A re q u e s t AD2 GPIO Controller AD1 ADn 38.4 Neg Analog mux AD0 Pos Analog mux E x te rn a l R e f.
PAGE 996
ATSAM4L8/L4/L2 peripheral function. If I/O lines of the ADCIFE are not used by the application, they can be used for other purposes by the I/O controller. 38.5.2 Power Management If the CPU enters a power reduction mode that disables clocks used by the ADCIFE, the ADCIFE will stop functioning and resume operation after the system wakes up from power reduction mode.
PAGE 997
ATSAM4L8/L4/L2 Note that all ADCIFE controls will be ignored until SR.EN goes to ‘1’. Before the ADCIFE can be used, the Internal Reference Voltage signal must be selected by writing the CFG.REFSEL field and the I/O Controller must be configured correctly. Refer to I/O Controller section for details. The user must also configure the frequency range by writting the CFG.SPEED field.
PAGE 998
ATSAM4L8/L4/L2 Note that the ADC works differentially in single-ended mode as well, as long as the positive input has a higher voltage than the negative. 38.6.5 ADC Clock Configuration The ADCIFE generates an internal clock named CLK_ADC that is used by the Analog-to-Digital Converter cell to perform conversions. The CLK_ADC is selected by writing to the CLKSEL bit in the Configuration Register (CFG).
PAGE 999
ATSAM4L8/L4/L2 (CR.DIS). Another way to reset ADCIFE is to write a one in the SWRST field of the Control Register (CR.SWRST). In both cases configuration registers won’t be affected. 38.6.9 Analog Reference Refer to Section 42. ”Electrical Characteristics” on page 1120. The ADC allows the possibility to select several voltage reference (Vref). • An internal 1.0V voltage reference derived from the internal 1.1V • 0.625*Vcc (to get 1.0V when Vcc=1.6V) • Vcc/2 • 2 external reference inputs 38.6.
PAGE 1000
ATSAM4L8/L4/L2 Operating mode Unipolar mode without gain and without hysteresis Unipolar mode without gain and with hysteresis (zoomrange[2]=1) Unipolar mode without hysteresis and gain =2n Unipolar mode without hysteresis and with division by 2 Unipolar mode with hysteresis and gain =2n Unipolar mode with hysteresis and with division by 2 38.6.13 Input range 0 to Vref -0.05*vref to 0.
PAGE 1001
ATSAM4L8/L4/L2 from the Timer Busy field of the SR register (SR.TBUSY): 0 means stopped, 1 means running. In addition when the internal timer is running, if ITIMER.ITMC is written to change the internal timer timeout frequency, the internal counter is cleared to avoid rollover phenomena. Note: It is possible to generate an internal timer event each GCLK period by writing 0 in ITIMER.ITMC and by selecting the internal timer as a STRIG source 38.6.
PAGE 1002
ATSAM4L8/L4/L2 Figure 38-3.
PAGE 1003
ATSAM4L8/L4/L2 Table 38-3. Window Monitor Modes WM field in WCFGy Modes 0 0 0 No window mode (default) 0 0 1 Mode 1: active when result > LT 0 1 0 Mode 2: active when result < HT 0 1 1 Mode 3: active when LT < result < HT 1 0 0 Mode 4: active when (!(LT < result < HT)) 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved Note: Comparisons are performed regardless with the SEQCFG.HWLA setting (half word left adjust). 38.6.
PAGE 1004
ATSAM4L8/L4/L2 38.7 User Interface Table 38-5.
PAGE 1005
ATSAM4L8/L4/L2 38.7.1 Name: Control Register CR Access Type: Write-Only Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - BGREQDIS BGREQEN DIS EN 7 6 5 4 3 2 1 0 - - REFBUFDIS REFBUFEN STRIG TSTART TSTOP SWRST Writing a zero to any of those bits in this register has no effect.
PAGE 1006
ATSAM4L8/L4/L2 • TSTART:Internal timer start bit Writing a one to this bit starts the internal timer Reading this bit always returns 0 Note: The internal timer status can be read in the RUNT field of the SR register • TSTOP:Internal timer stop bit Writing a one to this bit stops the internal timer Reading this bit always returns 0 Note: The internal timer status can be read in the RUNT field of the SR register • SWRST: Software reset Writing a zero to this bit has no effect.
PAGE 1007
ATSAM4L8/L4/L2 38.7.
PAGE 1008
ATSAM4L8/L4/L2 • SPEED: ADC current reduction SPEED Max speed 00 300 ksps 01 225 ksps 10 150 ksps 11 75 ksps • REFSEL: ADC Reference selection REFSEL Description 000 Internal 1.0V (10/11*bandgap) 001 0.
PAGE 1009
ATSAM4L8/L4/L2 38.7.
PAGE 1010
ATSAM4L8/L4/L2 • SMTRG:Sequencer missed trigger event This bit is set when a sequencer trigger event is missed This bit is cleared when the corresponding bit in SCR is written to one • WM:Window monitor This bit is set when the watched result value goes to the defined window This bit is cleared when the corresponding bit in SCR is written to one • LOVR:Sequencer last converted value overrun This bit is set when an overrun error occurs on the LCV register This bit is cleared when the corresponding bit in SCR
PAGE 1011
ATSAM4L8/L4/L2 38.7.4 Name: Status Clear Register SCR Access Type: Write-Only Offset: 0x0C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - TTO - SMTRG WM LOVR SEOC Writing a zero to a bit in this register has no effect.
PAGE 1012
ATSAM4L8/L4/L2 38.7.
PAGE 1013
ATSAM4L8/L4/L2 • ZOOMRANGE: Zoom shift/unipolar reference source selection ZOOMRANGE Mode Comment 000 Select Vref for shift cycle All modes except zoom and unipolar with hysteresis 001 Select Vdd/4 for shift cycle Zoom mode 010 Select Vdd/2 for shift cycle Zoom mode 011 Select 3*Vdd/4 for shift cycle Zoom mode 1XX Select 0.
PAGE 1014
ATSAM4L8/L4/L2 BIPOLAR INTERNAL MUXPOS Positive input to ADC X X0 0100 AD4 X X0 0101 AD5 X X0 0110 AD6 X X0 0111 AD7 X X0 1000 AD8 X X0 1001 AD9 X X0 1010 AD10 X X0 1011 AD11 X X0 1100 AD12 X X0 1101 AD13 X X0 1110 AD14 X X0 1111 Bandgap X X1 X000 Not used X X1 X001 Bandgap X X1 X010 Scaled Vcc, Vcc/10 X X1 X011 DAC internal X X1 X100 Not used X X1 X101 Not used X X1 X110 Vsingle = 0.
PAGE 1015
ATSAM4L8/L4/L2 • INTERNAL: Internal Voltage Sources Selection INTERNAL Positive Internal Selection Negative Internal Selection 00 Enables the primary/secondary voltage sources Enables the primary voltage sources 01 Enables the internal voltage sources Enables the primary voltage sources 10 Enables the primary/secondary voltage sources Enables the internal voltage sources 11 Enables the internal voltage sources Enables the internal voltage sources • RES: Resolution RES Resolution 0 12-bits
PAGE 1016
ATSAM4L8/L4/L2 • GAIN: Gain factor GAIN Gain factor 000 1x 001 2x 010 4x 011 8x 100 16 x 101 32 x 110 64 x 111 0,5 x • BIPOLAR: Bipolar Mode 1: Enables the differential mode 0: Enables the single-ended mode • HWLA: Half Word Left Adjust 1: Enables the HWLA mode 0: Disables the HWLA mode 1016 42023E–SAM–07/2013
PAGE 1017
ATSAM4L8/L4/L2 38.7.
PAGE 1018
ATSAM4L8/L4/L2 This register is used for DMA transfers to the ADCIFE module. The first word transmitted is the general configuration. If the MSB bit is set to one, a second word will be transfered to complete the configuration so that use the Window Mode. If the MSB bit is set to zero, the configuration is completed. The second word is only used when the window mode is needed. In this case, its MSB bit is always set to zero (configuration completed).
PAGE 1019
ATSAM4L8/L4/L2 38.7.
PAGE 1020
ATSAM4L8/L4/L2 38.7.
PAGE 1021
ATSAM4L8/L4/L2 38.7.
PAGE 1022
ATSAM4L8/L4/L2 38.7.
PAGE 1023
ATSAM4L8/L4/L2 38.7.11 Name: Sequencer Last Converted Value LCV Access Type: Read-Only Offset: 0x2C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 15 LCNC 14 13 LCPC 12 11 10 9 8 3 2 1 0 LCV[15:0] 7 6 5 4 LCV[7:0] • LCNC: Last converted negative channel This field is set by hardware to the last negative channel converted, i.e. what negative channel the LCV represents.
PAGE 1024
ATSAM4L8/L4/L2 38.7.12 Name: Interrupt Enable Register IER Access Type: Write-Only Offset: 0x30 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - 7 6 5 4 3 2 1 0 - - TTO - SMTRG WM LOVR SEOC Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
PAGE 1025
ATSAM4L8/L4/L2 38.7.13 Name: Interrupt Disable Register IDR Access Type: Write-Only Offset: 0x34 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - 7 6 5 4 3 2 1 0 - - TTO - SMTRG WM LOVR SEOC Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
PAGE 1026
ATSAM4L8/L4/L2 38.7.14 Name: Interrupt Mask Register IMR Access Type: Read-Only Offset: 0x38 Reset Value: 0x00000000 31 30 29 28 - - - 23 22 21 20 - - - - 15 14 13 12 - - - 7 6 5 4 - - TTO - 27 26 25 24 - - - 18 17 16 - - - 10 9 8 - - - 3 2 1 0 SMTRG WM LOVR SEOC 19 11 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one.
PAGE 1027
ATSAM4L8/L4/L2 38.7.15 Name: Calibration Register CALIB Access Type: Read/Write Offset: 0x3C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - FCD 15 14 13 12 11 10 9 8 - - - BIASSEL 3 2 1 0 BIASCAL 7 6 5 4 CALIB • FCD: Flash Calibration Done Set to one when CALIB and BIASCAL have been updated by the flash fuses after a reset.
PAGE 1028
ATSAM4L8/L4/L2 • CALIB: Calibration value CALIB Value Description 7 S1 MSB 4 S1 LSB 3 S2 MSB 0 S2 LSB 1028 42023E–SAM–07/2013
PAGE 1029
ATSAM4L8/L4/L2 38.7.16 Name: Module Version VERSION Access Type: Read-Only Offset: 0x40 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
PAGE 1030
ATSAM4L8/L4/L2 38.7.
PAGE 1031
ATSAM4L8/L4/L2 38.8 Module Configuration The specific configuration for each ADCIFE instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Refer to Section 10. ”Power Manager (PM)” on page 108 for details. Table 38-6. ADCIFE Configuration Feature ADCIFE External Ref 2 connection DACC OUT output Table 38-7.
PAGE 1032
ATSAM4L8/L4/L2 39. LCD Controller (LCDCA) Rev: 1.0.0.0 39.1 Features • • • • • • • • • • • • • • • • • • 39.
PAGE 1033
ATSAM4L8/L4/L2 Dedicated Low Power Waveform, Contrast Control, Extended Interrupt Mode, ASCII Character Mapping, automated modes... are defined to offload the CPU, reduce interrupts and reduce power consumption. To reduce hardware design complexity, the module includes integrated LCD buffers, an integrated power supply voltage. 39.3 Block Diagram Figure 39-2.
PAGE 1034
ATSAM4L8/L4/L2 39.5.1 I/O Lines The LCDCA pins (SEGx and COMy) are multiplexed with other peripherals. The user must first configure the I/O Controller to give control of the pins to the LCDCA. VLCD, BIAS1, BIAS2, CAPL, CAPH are not multiplexed. 39.5.2 Power Management This module can control the LCD display while CLK_LCDCA is disabled but stops functioning when CLK_LCD (32KHz) is disabled.
PAGE 1035
ATSAM4L8/L4/L2 Addressing COM0 starts a frame by driving an opposite phase with large amplitude on COM0 as against non addressed COM terminals. Non-energized segments are in phase with the addressed COM0, and energized segments have opposite phase and large amplitude (refer to ”Operating modes” on page 1035). Shadow display memory bits are multiplexed into the decoder.
PAGE 1036
ATSAM4L8/L4/L2 Figure 39-4. Driving a LCD With One Common Line 39.6.2.2 1/2 Duty and 1/3 Bias For a LCD with two common terminals (1/2 duty) a more complex waveform must be used to individually control segments. SEG0-COM0 is the voltage across a segment that is ON and SEG0-COM1 is the voltage across a segment that is OFF. Figure 39-5. Driving an LCD With Two Common Lines 39.6.2.3 1/3 Duty and 1/3 Bias 1/3 bias is usually recommended for LCD with three common terminals (1/3 duty).
PAGE 1037
ATSAM4L8/L4/L2 Figure 39-6. Driving a LCD With Three Common Lines 39.6.2.4 1/4 Duty and 1/3 Bias 1/3 bias is optimal for LCD with four common terminals (1/4 duty). SEG0-COM0 is the voltage across a segment that is ON and SEG0-COM1 is the voltage across a segment that is OFF. Figure 39-7.
PAGE 1038
ATSAM4L8/L4/L2 When LCD controller is disabled all segment and common terminals are driven to GND, discharging the LCD in order to avoid DC voltage across the segments and a slowly fading image. Data in the display memory is preserved. In order to restart correctly, it is preferrable to disable all functions (blinking, FCx,...) before disabling LCD controller. 39.6.4 Waveform Modes To reduce toggle activity and hence power consumption, write a zero to the Waveform Mode (CFG.
PAGE 1039
ATSAM4L8/L4/L2 The Clock Division field (CLKDIV) in TIM register defines the division ratio in the clock divider. This gives extra flexibility in frame rate setting. F ( CLK_LCD ) FrameRate = ---------------------------------------------------------------------------------------------------( 1 – WMOD ) ( K × N × ( 1 + CLKDIV ) × 2 ) Where: N = prescaler divider (8 or 16). K = 8 for 1/4, 1/2 and static duty. K = 6 for 1/3 duty. WMOD = 0 in low power waveform mode, = 1 in standard waveform mode. Table 39-4.
PAGE 1040
ATSAM4L8/L4/L2 Each frame counter is enabled by writing a one to Frame Counter x Enable (CR.FCxEN) and disabled by writing a one to Frame Counter x Disable (CR.FCxDIS).Frame counter must be disabled (SR.FCxS=0) before the update of its associated TIM.FCx value. 39.6.6 39.6.6.1 CPU Display Memory Access Direct Access CPU can access display memory in direct access by writing to Data Register Low x (DRLx) and Data Register High x (DRHx). Read-modify-write operation is then required to update few bits.
PAGE 1041
ATSAM4L8/L4/L2 Up to eight segments can be selected individually to blink. Each bit in Blink Segment Selection x field (BCFG.BSSx) selects a segment for blinking. If BSS0[y]=1, segment connected to SEG0/COMy is selected to blink. If BSS1[y]=1, segment connected to SEG1/COMy is selected to blink. A segment will blink if its corresponding bit is one in the display memory, otherwise it remains OFF. The blink frequency is defined by the number of frames (FCx in TIM register) between each state ON/OFF.
PAGE 1042
ATSAM4L8/L4/L2 The shifting period is defined by the number of frame in TIM.FCx. The frame counter is selected by writing its number in CSRCFG.FCS field. If frame rate is 50Hz (20ms) in standard waveform mode, shifting period is 160ms up to 5.1s. Initial value of circular shift register must be written in CSRCFG.DATA, the direction is defined by CSRCFG.DIR bit (0 for left, 1 for right) and circular shift register operation is started by writing a one to CR.CSTART. Once enabled, data is shifted every TIM.
PAGE 1043
ATSAM4L8/L4/L2 Figure 39-10. Type of Digit Supported 7-Segment - 3 COM term. - 3 SEG term. 7-Segment - 4 COM term. - 2 SEG term. 14-Segment - 4 COM term. - 4 SEG term. 16-Segment - 3 COM term. - 6 SEG term. Character mapping saves CPU execution time and allows a fast return to sleep mode after display update.
PAGE 1044
ATSAM4L8/L4/L2 Table 39-8.
PAGE 1045
ATSAM4L8/L4/L2 Table 39-9.
PAGE 1046
ATSAM4L8/L4/L2 Table 39-10.
PAGE 1047
ATSAM4L8/L4/L2 39.6.11 Automated Character Mapping Displaying predefined character strings can be automated using the Peripheral DMA Controller (PDCA). Two modes are available, defined by MODE bit in Automated Character Mapping Configuration register (ACMCFG): • MODE=0, the sequential character string display mode is selected • MODE=1, the scrolling of character string display mode is selected 39.6.11.
PAGE 1048
ATSAM4L8/L4/L2 Figure 39-11. Sequential Character String Example (DIGN = 5, frame rate = 50Hz, TIM.ACMFC = 31) String = ’HELLOWORLDTHIS IS AUTOMATED ’ H E L L O W O R L D 10.2 T H I S 15.3 I S 20.4 A U T O 25.5 A T E D 0 5.1 M t (s) 39.6.11.2 Scrolling of Characters String This mode displays the same characters string periodically shifted by one character in left direction. The configuration is: • specify the number of digit (ACMCFG.
PAGE 1049
ATSAM4L8/L4/L2 character string. Number of transfer must be a multiple of STEPS to get a complete scrolling of the string. Blank characters can be added to string to create a complete scrolling. The frame counter selected (TIM.FCx) defines the number of frames between each PDCA transfer, refer to ”Sequential Characters String Display” on page 1047 Figure 39-12.
PAGE 1050
ATSAM4L8/L4/L2 • DMASK[7:0], each bit is a mask for DATA field. When DMASK[x]=1, DATA[x] is not written to display memory, • OFF[4:0], byte offset in display memory (see Figure 39-3 on page 1035). To update more than 8 segments, PDCA must transfer multiple words before shadow memory is updated. This number of words must also be written in SIZE field in Automated Bit Mapping Configuration register (ABMCFG), it indicates the number of writes in display memory to form a frame.
PAGE 1051
ATSAM4L8/L4/L2 Wake up mechanism is enabled by writing a one to the Wake up Enable (WEN) bit in configuration register. It is disabled by writing a one to the Wake up Disable bit (WDIS). Moreover LCDCA interrupt request must not be masked (see previous section) and LCDCA bit in Asynchronous Wake Up Enable register (AWEN.LCDCA) must be set to one (see Power Manager chapter). Wake up signal is generated when frame counter 0 rolls over.
PAGE 1052
ATSAM4L8/L4/L2 Figure 39-14. Internal and External Bias Generation Internal Generation (static or 1/3 Bias) Device External Generation (static) Device VCC VCC CAPH External Generation (example) (1/3 Bias) Device VCC VCC VCC VCC CAPH CAPH (1) 100 nF CAPL CAPL CAPL Ext. VLCD Ext. VLCD VLCD VLCD (2) VLCD BIASH BIASH 100 nF (1) BIASL BIASL 100 nF BIASH BIASL Decoupling capacitors (1) Decoupling capacitor 100 nF (1) GND GND GND (1) Values are given for design guidance only.
PAGE 1053
ATSAM4L8/L4/L2 39.7 User Interface Table 39-12.
PAGE 1054
ATSAM4L8/L4/L2 39.7.1 Name: Control Register CR Access Type: Write-Only Offset: 0x00 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - CSTOP CSTART BSTOP BSTART WEN WDIS CDM 7 6 5 4 3 2 1 0 FC2EN FC2DIS FC1EN FC1DIS FC0EN FC0DIS EN DIS Writing a zero to a bit in this register has no effect.
PAGE 1055
ATSAM4L8/L4/L2 • DIS: Disable Writing a one to this bit disables the LCD controller.
PAGE 1056
ATSAM4L8/L4/L2 39.7.2 Name: Configuration Register CFG Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 31 30 29 28 - - 23 22 - - 15 14 13 12 - - - 7 6 - - 27 26 25 24 18 17 16 11 10 9 8 - - - 5 4 3 2 1 0 - - LOCK BLANK WMOD XBIAS NSU 21 20 19 FCST DUTY NSU, DUTY, WMOD and XBIAS shall not be modified when LCDCA is enabled (SR.EN=1). • NSU: Number of Segment Terminals in Use This field indicates the number of segment terminals in use.
PAGE 1057
ATSAM4L8/L4/L2 If this bit is modified during display operation the waveform mode is applied at the beginning of next frame. • XBIAS: External Bias Generation 0:Internal bias is used. 1:External bias is used.
PAGE 1058
ATSAM4L8/L4/L2 39.7.3 Name: Timing Register TIM Access Type: Read/Write Offset: 0x08 Reset Value: 0x00000000 • • • • • 31 30 29 28 - - - 23 22 21 - - - 15 14 13 - - FC0PB 7 6 5 4 - - - - 27 26 25 24 17 16 9 8 1 0 FC2 20 19 18 FC1 12 11 10 FC0 3 2 CLKDIV PRESC CLKDIV and PRESC shall not be modified when LCD controller is enabled. FCx shall not be modified when Frame Counter x is enabled.
PAGE 1059
ATSAM4L8/L4/L2 39.7.4 Name: Status Register SR Access Type: Read-Only Offset: 0x0C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - CPS 7 6 5 4 3 2 1 0 CSRS BLKS WEN EN FC2S FC1S FC0S FC0R • CPS: Charge Pump Status 0: Charge pump is inactive or not ready. 1: Charge pump is ready. • CSRS: Circular Shift Register Status 0: CSR is not running. 1: CSR is running.
PAGE 1060
ATSAM4L8/L4/L2 39.7.5 Name: Status Clear Register SCR Access Type: Write-Only Offset: 0x10 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - FC0R Writing a zero to a bit in this register has no effect. Writing a one to a bit clears the corresponding SR bit.
PAGE 1061
ATSAM4L8/L4/L2 39.7.6 Name: Data Register Low DRLx Access Type: Read/Write Offset: 0x14+8*x Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DATA[31:24] 23 22 21 20 DATA[23:16] 15 14 13 12 DATA[15:8] 7 6 5 4 DATA[7:0] Display memory is not initialized at startup. • DATA: Segments Value Each bit defines the segment value in display memory.
PAGE 1062
ATSAM4L8/L4/L2 39.7.7 Name: Data Register High DRHx Access Type: Read/Write Offset: 0x18+8*x Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 DATA • DATA: Segments Value Each bit defines the segment value in display memory.
PAGE 1063
ATSAM4L8/L4/L2 39.7.8 Name: Indirect Access Data Register IADR Access Type: Write-Only Offset: 0x34 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - 15 14 13 OFF 12 11 10 9 8 3 2 1 0 DMASK 7 6 5 4 DATA • OFF: Byte Offset Byte offset in display memory. • DMASK: Data Mask Each bit is a mask for DATA field. When DMASK[x]=1, DATA[x] is not written to display memory.
PAGE 1064
ATSAM4L8/L4/L2 39.7.9 Name: Blink Configuration Register BCFG Access Type: Read/Write Offset: 0x38 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 1 0 BSS1 BSS0 7 6 5 4 3 - - - - - 2 FCS MODE • BSS1: Blink Segment Selection 1 If BSS1[x] is set, segment connected to SEG1/COMx is selected.
PAGE 1065
ATSAM4L8/L4/L2 39.7.10 Name: Circular Shift Register Configuration CSRCFG Access Type: Read/Write Offset: 0x3C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 DATA 7 6 - - 5 4 SIZE FCS DIR • DATA: Circular Shift Register Value • SIZE: Size Defines the size of the circular shift register, (SIZE + 1) bits. • FCS: Frame Counter Selection Table 39-15.
PAGE 1066
ATSAM4L8/L4/L2 39.7.11 Name: Character Mapping Configuration Register CMCFG Access Type: Read/Write Offset: 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - 7 6 5 4 3 2 1 0 - - - - - STSEG TDG DREV • STSEG: Start Segment Defines the first segment terminal used to write the decoded display. • TDG: Type of Digit Table 39-16.
PAGE 1067
ATSAM4L8/L4/L2 39.7.
PAGE 1068
ATSAM4L8/L4/L2 39.7.13 Name: Automated Character Mapping Configuration Register ACMCFG Access Type: Read/Write Offset: 0x48 Reset Value: 0x00000000 31 30 29 28 - - - - 23 22 21 20 27 26 25 24 DIGN 19 18 17 16 11 10 9 8 2 1 0 STEPS 15 14 - - 7 6 - 13 12 STSEG 5 TDG 4 3 DREV MODE FCS EN • DIGN: Digit Number Defines the number of digit used (must be >1). • STEPS: Scrolling Steps Defines the number of steps in scrolling mode.
PAGE 1069
ATSAM4L8/L4/L2 • FCS: Frame Counter Selection Table 39-18. Frame Counter Selection FCS Frame Counter 00 FC0 01 FC1 10 FC2 11 reserved • EN: Enable 0: Automated character mapping is disabled. 1: Automated character mapping is enabled.
PAGE 1070
ATSAM4L8/L4/L2 39.7.
PAGE 1071
ATSAM4L8/L4/L2 39.7.15 Name: Automated Bit Mapping Configuration Register ABMCFG Access Type: Read/Write Offset: 0x50 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - 15 14 13 12 11 10 9 8 - - - 7 6 5 4 3 1 0 - - - - - SIZE 2 FCS EN • SIZE: Size Defines the number of PDCA writes to ABMDR to form a frame (must be >1). • FCS: Frame Counter Selection Table 39-19.
PAGE 1072
ATSAM4L8/L4/L2 39.7.16 Name: Automated Bit Mapping Data Register ABMDR Access Type: Write-Only Offset: 0x54 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - 15 14 13 OFF 12 11 10 9 8 3 2 1 0 DMASK 7 6 5 4 DATA • OFF: Byte Offset Byte offset in display memory. • DMASK: Data Mask Each bit is a mask for DATA field. When DMASK[x]=1, DATA[x] is not written to display memory.
PAGE 1073
ATSAM4L8/L4/L2 39.7.17 Name: Interrupt Enable Register IER Access Type: Write-Only Offset: 0x58 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - FC0R Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
PAGE 1074
ATSAM4L8/L4/L2 39.7.18 Name: Interrupt Disable Register IDR Access Type: Write-Only Offset: 0x5C Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - FC0R Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
PAGE 1075
ATSAM4L8/L4/L2 39.7.19 Name: Interrupt Mask Register IMR Access Type: Read-Only Offset: 0x60 Reset Value: 0x00000000 31 30 29 28 - - - - 23 22 21 20 - - - - 15 14 13 12 - - - - 7 6 5 4 - - - - 27 26 25 24 - - - 18 17 16 - - - 10 9 8 - - - 3 2 1 0 - - - FC0R 19 11 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one.
PAGE 1076
ATSAM4L8/L4/L2 39.7.20 Name: Module Version VERSION Access Type: Read-Only Offset: 0x64 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 1 0 VARIANT 11 10 VERSION[11:8] 3 2 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
PAGE 1077
ATSAM4L8/L4/L2 39.8 Module Configuration The specific configuration for LCDCA is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Refer to Section 10. ”Power Manager (PM)” on page 108 for details. Table 39-20. LCDCA Clocks Clock Name Description CLK_LCDCA LCDCA bus interface clock CLK_LCD LCD 32kHz clock Table 39-21.
PAGE 1078
ATSAM4L8/L4/L2 Table 39-22.
PAGE 1079
ATSAM4L8/L4/L2 Table 39-22.
PAGE 1080
ATSAM4L8/L4/L2 40. Parallel Capture (PARC) Rev: 1.0.0.0 40.1 Features • • • • • 40.2 Captures 8-bits data with external input clock External data enables supported Various enable conditions Peripheral DMA supported Peripheral events supported Overview The Parallel Capture peripheral samples an external 8-bit bus with an external input clock. It can be connected to a CMOS digital image sensor, an ADC, a DSP synchronous port,... The number of PARC modules implemented is device specific.
PAGE 1081
ATSAM4L8/L4/L2 40.5.1 I/O Lines The PARC pins are multiplexed with other peripherals. The user must first configure the I/O Controller to give control of the pins to the PARC. 40.5.2 Power Management PARC stops functioning when the system enters a sleep mode that disables its clock. 40.5.3 Clocks The clock for PARC (CLK_PARC) is generated by the Power Manager.
PAGE 1082
ATSAM4L8/L4/L2 An overrun condition is detected if RHR is not read before internal buffer is full. Data in RHR is corrupted and Overrun bit is set to one in the Status Register (SR.OVR). 40.6.2 Peripheral DMA PARC can be associated to a Peripheral DMA Controller (PDCA) channel. It will then perform data transfer from PARC to a memory buffer without any CPU intervention (see PDCA chapter for channel configuration). PDCA and PARC data size must be equal, if CFG.
PAGE 1083
ATSAM4L8/L4/L2 Figure 40-2.
PAGE 1084
ATSAM4L8/L4/L2 40.7 User Interface Table 40-2.
PAGE 1085
ATSAM4L8/L4/L2 40.7.1 Name: Configuration Register CFG Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 • • • • • 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 ODD HALF EDGE EMODE SMODE DSIZE To avoid unexpected behavior CFG must be written when PARC is disabled. ODD: Odd Capture 0: only bytes with even index are captured.
PAGE 1086
ATSAM4L8/L4/L2 • DSIZE: Data Size DSIZE Size 0 0 data size in RHR is a byte (8-bit) 0 1 data size in RHR is a half-word (16-bit) 1 0 data size in RHR is a word (32-bit) 1 1 data size in RHR is a word (32-bit) 1086 42023E–SAM–07/2013
PAGE 1087
ATSAM4L8/L4/L2 40.7.2 Name: Control Register CR Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - STOP START DIS EN • STOP: Stop Capture Writing a zero to this bit has no effect. Writing a one to this bit disables data capture. This bit always reads as zero.
PAGE 1088
ATSAM4L8/L4/L2 40.7.3 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x08 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - OVR DRDY - - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
PAGE 1089
ATSAM4L8/L4/L2 40.7.4 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x0C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - OVR DRDY - - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
PAGE 1090
ATSAM4L8/L4/L2 40.7.5 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - OVR DRDY - - 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
PAGE 1091
ATSAM4L8/L4/L2 40.7.6 Name: Status Register SR Access Type: Read-only Offset: 0x14 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - OVR DRDY CS EN • OVR: Overrun 0: No overrun error occurred since last read of RHR. 1: At least one overrun error occurred since last read of RHR.
PAGE 1092
ATSAM4L8/L4/L2 40.7.7 Name: Interrupt Status Clear Register ICR Access Type: Write-only Offset: 0x18 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - OVR DRDY - - Writing a zero to a bit in this register has no effect.
PAGE 1093
ATSAM4L8/L4/L2 40.7.8 Name: Receive Holding Register RHR Access Type: Read/Write Offset: 0x1C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CDATA[31:24] 23 22 21 20 CDATA[23:16] 15 14 13 12 CDATA[15:8] 7 6 5 4 CDATA[7:0] • CDATA: Captured Data Captured data size is defined by CR.DSIZE.
PAGE 1094
ATSAM4L8/L4/L2 40.7.9 Name: Version Register VERSION Access Type: Read-only Offset: 0x20 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
PAGE 1095
ATSAM4L8/L4/L2 40.8 Module Configuration The specific configuration for each PARC instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Refer to Section 10. ”Power Manager (PM)” on page 108 for details. Table 40-3. PARC Clock Name Module Name Clock Name Description PARC CLK_PARC Peripheral clock for PARC Table 40-4.
PAGE 1096
ATSAM4L8/L4/L2 41. Cyclic Redundancy Check Calculation Unit (CRCCU) Rev: 2.0.2.0 41.1 Features • Performs Cyclic Redundancy Check Operation on Memory Area • Single AHB Master Interface • APB Configuration Interface 41.2 Overview The CRCCU performs CRC check on memory area. 41.3 Block Diagram Figure 41-1. CRCCU Block Diagram APB Interface CLK_CRCCU_APB AHB DMA CRC irq CLK_CRCCU_AHB 41.
PAGE 1097
ATSAM4L8/L4/L2 41.5 Functional Description Once configured (Mode Register, MR) and enabled by writing a one to MR.ENABLE, the CRC engine performs a checksum computation from memory data. CRC computation is performed from LSB to MSB bit. Three different polynomials (CCIT802.3, CASTAGNOLI, CCIT16) can be configured in MR.PTYPE. CRCCU uses its own DMA mechanism to read memory area (Flash or RAM area). DMA uses a descriptor located in memory area.
PAGE 1098
ATSAM4L8/L4/L2 To compute CRC for a memory size larger than 256Kbytes of for non-contiguous memory area, CRCCU can be enabled again for a new memory area. CRC will be updated accordingly. Conversely, set CR.RESET to one to reset the intermediate CRC to its default value (0xFFFFFFFF).
PAGE 1099
ATSAM4L8/L4/L2 41.6 User Interface Table 41-1.
PAGE 1100
ATSAM4L8/L4/L2 41.6.1 Name: Descriptor Base Address Register DSCR Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 DSCR[22:15] 23 22 21 20 DSCR[14:7] 15 14 13 12 DSCR[6:0] - 7 6 5 4 3 2 1 0 - - - - - - - - • DSCR: Description Base Address Address of CRC descriptor (512-byte aligned).
PAGE 1101
ATSAM4L8/L4/L2 41.6.2 Name: DMA Enable Register DMAEN Access Type: Write-only Offset: 0x08 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - DMAEN • DMAEN: DMA Enable Write a one to enable DMA channel. Writing a zero has no effect.
PAGE 1102
ATSAM4L8/L4/L2 41.6.3 Name: DMA Disable Register DMADIS Access Type: Write-only Offset: 0x0C Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - DMADIS • DMADIS: DMA Disable Write a one to disable DMA channel. Writing a zero has no effect.
PAGE 1103
ATSAM4L8/L4/L2 41.6.4 Name: DMA Status Register DMASR Access Type: Read-only Offset: 0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - DMASR • DMASR: DMA Channel Status 0: DMA channel is disabled. 1: DMA channel is enabled.
PAGE 1104
ATSAM4L8/L4/L2 41.6.5 Name: DMA Interrupt Enable Register DMAIER Access Type: Write-only Offset: 0x14 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - DMAIER • DMAIER: DMA Interrupt Enable Write a one to enable DMA interrupt. Writing a zero has no effect.
PAGE 1105
ATSAM4L8/L4/L2 41.6.6 Name: DMA Interrupt Disable Register DMAIDR Access Type: Write-only Offset: 0x18 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - DMAIDR • DMAIDR: DMA Interrupt Disable Write a one to disable DMA interrupt. Writing a zero has no effect.
PAGE 1106
ATSAM4L8/L4/L2 41.6.7 Name: DMA Interrupt Mask Register DMAIMR Access Type: Read-only Offset: 0x1C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - DMAIMR • DMAIMR: DMA Interrupt Mask Status 0: DMA interrupt is disabled. 1: DMA interrupt is enabled.
PAGE 1107
ATSAM4L8/L4/L2 41.6.8 Name: DMA Interrupt Status Register DMAISR Access Type: Read-only Offset: 0x20 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - DMAISR • DMAISR: DMA Interrupt Status 0: No DMA transfer or in-progress. 1: DMA transfer is completed. This bit is set to zero when DMAISR is read.
PAGE 1108
ATSAM4L8/L4/L2 41.6.9 Name: Control Register CR Access Type: Write-only Offset: 0x34 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - RESET • RESET: Reset CRCComputation Write a one to reset SR. Writing a zero has no effect.
PAGE 1109
ATSAM4L8/L4/L2 41.6.10 Name: Mode Register MR Access Type: Read/Write Offset: 0x38 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 COMPARE ENABLE DIVIDER PTYPE • DIVIDER: Bandwidth Divider DMA bandwidth, required for CRC computation, is divided by 2^(DIVIDER+1).
PAGE 1110
ATSAM4L8/L4/L2 41.6.11 Name: Status Register SR Access Type: Read-only Offset: 0x3C Reset Value: 0xFFFFFFFF 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CRC[31:24] 23 22 21 20 CRC[23:16] 15 14 13 12 CRC[15:8] 7 6 5 4 CRC[7:0] • CRC: Cyclic Redundancy Check Value CRC computation result. If MR.COMPARE=1, SR is not readable.
PAGE 1111
ATSAM4L8/L4/L2 41.6.12 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x40 Reset Value: – 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - ERRIER Writing a zero to a bit in this register has no effect.
PAGE 1112
ATSAM4L8/L4/L2 41.6.13 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x44 Reset Value: – 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - ERRIDR Writing a zero to a bit in this register has no effect.
PAGE 1113
ATSAM4L8/L4/L2 41.6.14 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x48 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - ERRIMR 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. This bit is cleared when the corresponding bit in IDR is written to one.
PAGE 1114
ATSAM4L8/L4/L2 41.6.15 Name: Interrupt Status Register ISR Access Type: Read-only Offset: 0x4C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - ERRISR • ERRISR: CRC Error Interrupt Status 0: No CRC error 1: CRC error, CRC computed and CRC stored are different. ERRISR is cleared when this register is read.
PAGE 1115
ATSAM4L8/L4/L2 41.6.16 Name: Version Register VERSION Access Type: Read-only Offset: 0xFC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - 15 14 13 12 11 - - - - 7 6 5 4 VARIANT 10 9 8 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
PAGE 1116
ATSAM4L8/L4/L2 41.6.17 Name: Transfer Address Register ADDR Access Type: Read/Write Offset: DSCR Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR[31:24] 23 22 21 20 ADDR[23:16] 15 14 13 12 ADDR[15:8] 7 6 5 4 ADDR[7:0] • ADDR: Transfer Address Address of memory block to compute.
PAGE 1117
ATSAM4L8/L4/L2 41.6.
PAGE 1118
ATSAM4L8/L4/L2 41.6.19 Name: Transfer Reference Register CRC Access Type: Read/Write Offset: DSCR + 0x10 Reset Value: - 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 REFCRC[31:24] 23 22 21 20 19 REFCRC[23:16] 15 14 13 12 11 REFCRC[15:8] 7 6 5 4 3 REFCRC[7:0] • REFCRC: Reference CRC When compare mode is enabled, checksum is compared with this register.
PAGE 1119
ATSAM4L8/L4/L2 41.7 Module Configuration The specific configuration for each CRCCU instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Refer to Section 10. ”Power Manager (PM)” on page 108 for details. Table 41-3.
PAGE 1120
ATSAM4L8/L4/L2 42. Electrical Characteristics 42.1 Absolute Maximum Ratings* Table 42-1. Absolute Maximum Ratings Operating temperature..................................... -40°C to +85°C *NOTICE: Storage temperature...................................... -60°C to +150°C Voltage on input pins with respect to ground ..........................-0.3V to VVDD (1)+0.3V Total DC output current on all I/O pins VDDIO .........................................................................
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ATSAM4L8/L4/L2 Table 42-3. Supply Rise Rates and Order (1) VDDIO, VDDIN and VDDANA must be connected together and as a consequence, rise synchronously Rise Rate Symbol Parameter Min Max Unit VVDDIO DC supply peripheral I/Os 0.0001 2.5 V/µs VVDDIN DC supply peripheral I/Os and internal regulator 0.0001 2.5 V/µs VVDDANA Analog supply voltage 0.0001 2.5 V/µs 1. Comment These values are based on characterization. These values are not covered by test limits in production.
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ATSAM4L8/L4/L2 42.4 Maximum Clock Frequencies Table 42-4.
PAGE 1123
ATSAM4L8/L4/L2 Table 42-5. Maximum Clock Frequencies in Power Scaling Mode 1 and RUN Mode Symbol Parameter Description Max fCPU CPU clock frequency 12 fPBA PBA clock frequency 12 fPBB PBB clock frequency 12 fPBC PBC clock frequency 12 fPBD PBD clock frequency 12 fGCLK0 GCLK0 clock frequency DFLLIF main reference, GCLK0 pin 16.6 fGCLK1 GCLK1 clock frequency DFLLIF dithering and SSGreference, GCLK1 pin 16.6 fGCLK2 GCLK2 clock frequency AST, GCLK2 pin 6.
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ATSAM4L8/L4/L2 42.5 42.5.1 Power Consumption Power Scaling 0 and 2 The values in Table 42-6 are measured values of power consumption under the following conditions, except where noted: • Operating conditions for power scaling mode 0 and 2 – VVDDIN = 3.3V – Power Scaling mode 0 is used for CPU frequencies under 36MHz – Power Scaling mode 2 is used for CPU frequencies above 36MHz • Wake up time from low power modes is measured from the edge of the wakeup signal to the first instruction fetched in flash.
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ATSAM4L8/L4/L2 Table 42-6. ATSAM4L4/2 Current consumption and Wakeup time for power scaling mode 0 and 2 Max (1) 3817 4033 3934 4174 2341 2477 2437 2585 1758 1862 1847 1971 Linear mode 51 60 OSC32K and AST running Fast wake-up enable 5.9 8.7 4.7 7.6 3.1 5.1 AST and OSC32K stopped 2.2 4.2 OSC32K running AST running at 1kHz 1.5 3.1 AST and OSC32K stopped 0.9 1.
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ATSAM4L8/L4/L2 Table 42-7. ATSAM4L8 Current consumption and Wakeup time for power scaling mode 0 and 2 Max (1) 3817 4033 4050 4507 2341 2477 2525 2832 1758 1862 1925 1971 Linear mode 51 60 OSC32K and AST running Fast wake-up enable 6.
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ATSAM4L8/L4/L2 – All other peripheral clocks stopped • I/Os are inactive with internal pull-up • CPU is running on flash with 1 wait state • Low power cache enabled • BOD18 and BOD33 disabled Table 42-8.
PAGE 1128
ATSAM4L8/L4/L2 Table 42-9. ATSAM4L8 Current consumption and Wakeup time for power scaling mode 1 Mode Typical Wakeup Time Typ Max (1) 222 240 233 276 233 276 230 270 100 112 100 119 104 128 107 138 527 627 579 739 369 445 404 564 305 381 334 442 Linear mode 46 55 OSC32K and AST running Fast wake-up enable 5.
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ATSAM4L8/L4/L2 Table 42-10. Typical Power Consumption running CoreMark on CPU clock sources (1) RCSYS (MCSEL = 0) Power scaling mode 1 0.115 978 0.5 354 12 114 12 228 30 219 0.
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ATSAM4L8/L4/L2 Figure 42-1. Typical Power Consumption running Coremark (from above table) Note: For variable frequency oscillators, linear interpolation between high and low settings Figure 42-2.
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ATSAM4L8/L4/L2 42.5.3 Peripheral Power Consumption in Power Scaling mode 0 and 2 The values in Table 42-11 are measured values of power consumption under the following conditions: • Operating conditions, internal core supply (Figure 42-2) – VVDDIN = 3.
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ATSAM4L8/L4/L2 Table 42-11. Typical Current Consumption by Peripheral in Power Scaling Mode 0 and 2 (1) Peripheral IISC 1.0 SPI 1.9 TC 6.3 TWIM 1.5 TWIS 1.2 USART ADCIFE ACIFC Unit 8.5 (2) DACC 42.5.4 Typ Consumption Active 3.1 1.3 (2) 3.1 GLOC 0.4 ABDACB 0.7 TRNG 0.9 PARC 0.7 CATB 3.0 LCDCA 4.4 PDCA 1.0 CRCCU 0.3 USBC 1.5 PEVC 5.6 CHIPID 0.1 SCIF 6.4 FREQM 0.5 GPIO 7.1 BPM 0.9 BSCIF 4.6 AST 1.5 WDT 1.4 EIC 0.6 PICOUART 0.3 µA/MHz 1.
PAGE 1133
ATSAM4L8/L4/L2 • Operating conditions, internal core supply (Figure 42-2) – VVDDIN = 3.3V – VVDDCORE = 1.
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ATSAM4L8/L4/L2 Table 42-12. Typical Current Consumption by Peripheral in Power Scaling Mode 1 (1) Peripheral Typ Consumption Active IISC 0.5 SPI 1.1 TC 3.1 TWIM 0.8 TWIS 0.7 USART ADCIFE 4.4 (2) DACC ACIFC Unit 1.6 0.6 (2) 1.6 GLOC 0.1 ABDACB 0.3 TRNG 0.3 PARC 0.3 CATB 1.5 LCDCA 2.2 PDCA 0.4 CRCCU 0.3 USBC 0.9 PEVC 2.8 CHIPID 0.1 SCIF 3.1 FREQM 0.2 GPIO 3.4 BPM 0.4 BSCIF 2.3 AST 0.8 WDT 0.8 EIC 0.3 PICOUART 0.2 µA/MHz 1.
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ATSAM4L8/L4/L2 42.6 I/O Pin Characteristics 42.6.1 Normal I/O Pin Table 42-13. Normal I/O Pin Characteristics (1) Symbol Parameter RPULLUP Pull-up resistance (2) Conditions Min (2) Typ Max 40 kΩ 40 kΩ RPULLDOWN Pull-down resistance VIL Input low-level voltage -0.3 0.2 * VVDD VIH Input high-level voltage 0.8 * VVDD VVDD + 0.3 VOL Output low-level voltage VOH Output high-level voltage VVDD - 0.
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ATSAM4L8/L4/L2 3. These values are based on characterization. These values are not covered by test limits in production 42.6.2 High-drive I/O Pin : PA02, PC04, PC05, PC06 Table 42-14. High-drive I/O Pin Characteristics (1) Symbol Parameter Conditions Min (2) Typ Max RPULLUP Pull-up resistance RPULLDOWN Pull-down resistance(2) VIL Input low-level voltage -0.3 0.2 * VVDD VIH Input high-level voltage 0.8 * VVDD VVDD + 0.
PAGE 1137
ATSAM4L8/L4/L2 42.6.3 USB I/O Pin : PA25, PA26 Table 42-15. USB I/O Pin Characteristics in GPIO configuration (1) Symbol Parameter Conditions Min (2) Typ Max RPULLUP Pull-up resistance RPULLDOWN Pull-down resistance(2) VIL Input low-level voltage -0.3 0.2 * VVDD VIH Input high-level voltage 0.8 * VVDD VVDD + 0.
PAGE 1138
ATSAM4L8/L4/L2 Table 42-16. TWI Pin Characteristics in TWI configuration (1) Symbol Parameter Conditions Current Source(3) ICS Min Typ DRIVEH=0 0.5 DRIVEH=1 1 DRIVEH=2 1.5 DRIVEH=3 3 Max mA fMAX Max frequency(2) HsMode with Current source; DRIVEx=3, SLEW=0 Cbus = 400pF, VVDD = 1.68V tRISE Rise time(2) HsMode Mode, DRIVEx=3, SLEW=0 Cbus = 400pF, Rp = 440Ohm, VVDD = 1.68V 28 38 Standard Mode, DRIVEx=3, SLEW=0 Cbus = 400pF, Rp = 440Ohm, VVDD = 1.
PAGE 1139
ATSAM4L8/L4/L2 Table 42-17. TWI Pin Characteristics in GPIO configuration (1) Symbol Parameter Conditions OSRR0=0 OSRR0=1 Rise time(2) tRISE OSRR0=0 OSRR0=1 OSRR0=0 OSRR0=1 Fall time(2) tFALL OSRR0=0 OSRR0=1 Min Typ Max Units 18 ODCR0=0 1.68V
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ATSAM4L8/L4/L2 42.6.5 High Drive TWI Pin : PB00, PB01 Table 42-19. High Drive TWI Pin Characteristics in TWI configuration (1) Symbol Parameter Conditions (2) Min Typ Max RPULLUP Pull-up resistance RPULLDOWN Pull-down resistance(2) VIL Input low-level voltage -0.3 0.3 * VVDD VIH Input high-level voltage 0.7 * VVDD VVDD + 0.3 VOL Output low-level voltage VOH Output high-level voltage IOL ICS Output low-level current (3) Current Source(2) PB00, PB01 40 kΩ 40 kΩ VVDD - 0.
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ATSAM4L8/L4/L2 Table 42-20. High Drive TWI Pin Characteristics in GPIO configuration (1) Symbol Parameter Conditions Min Typ Max Units Pull-up resistance (2) 40 kΩ RPULLDOWN Pull-up resistance (2) 40 kΩ VIL Input low-level voltage -0.3 0.2 * VVDD VIH Input high-level voltage 0.8 * VVDD VVDD + 0.3 VOL Output low-level voltage VOH Output high-level voltage RPULLUP VVDD - 0.
PAGE 1142
ATSAM4L8/L4/L2 42.7 Oscillator Characteristics 42.7.1 Oscillator 0 (OSC0) Characteristics 42.7.1.1 Digital Clock Characteristics The following table describes the characteristics for the oscillator when a digital clock is applied on XIN. Table 42-22. Digital Clock Characteristics Symbol Parameter fCPXIN XIN clock frequency (1) tCPXIN XIN clock duty cycle(1) tSTARTUP Startup time 1. Conditions Min Typ 40 Max Units 50 MHz 60 % N/A cycles These values are based on simulation.
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ATSAM4L8/L4/L2 Table 42-23. Crystal Oscillator Characteristics Symbol CL Parameter Conditions Crystal load capacitance Typ 6 Crystal shunt capacitance Parasitic capacitor load CXOUT Parasitic capacitor load(2) tSTARTUP Startup time(1) Unit 7 pF (2) CXIN Max 18 (1) CSHUNT IOSC Min (1) 4.91 TQFP100 package 3.22 Current consumption(1) SCIF.OSCCTRL.GAIN = 2 30 000 (3) Active mode, f = 0.6MHz, SCIF.OSCCTRL.GAIN = 0 30 Active mode, f = 4MHz, SCIF.OSCCTRL.
PAGE 1144
ATSAM4L8/L4/L2 42.7.2 32kHz Crystal Oscillator (OSC32K) Characteristics Figure 42-3 and the equation above also applies to the 32kHz oscillator connection. The user must choose a crystal oscillator where the crystal load capacitance CL is within the range given in the table. The exact value of CL can then be found in the crystal datasheet. Table 42-24. Digital Clock Characteristics Symbol Parameter fCPXIN32 Conditions XIN32 clock frequency XIN32 clock duty cycle(1) Typ 40 Startup time tSTARTUP 1.
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ATSAM4L8/L4/L2 42.7.3 Phase Locked Loop (PLL) Characteristics Table 42-26. Phase Locked Loop Characteristics Symbol Parameter Conditions (1) fOUT Output frequency fIN Input frequency(1) IPLL Current consumption(1) tSTARTUP Startup time, from enabling the PLL until the PLL is locked(1) 1.
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ATSAM4L8/L4/L2 Table 42-27. Digital Frequency Locked Loop Characteristics Symbol tSTARTUP Parameter Startup time Conditions (1) Typ Within 90% of final values fREF = 32kHz, FINE lock, SSG disabled Lock time(1) tLOCK Min (2) Max Unit 100 µs 600 fREF = 32kHz, ACCURATE lock, dithering clock = RCSYS/2, SSG disabled(2) 1100 1. These values are based on simulation. These values are not covered by test limits in production or characterization. 2.
PAGE 1147
ATSAM4L8/L4/L2 42.7.7 1MHz RC Oscillator (RC1M) Characteristics Table 42-30. RC1M Oscillator Characteristics Symbol Parameter Conditions (1) fOUT Output frequency IRC1M Current consumption (2) Duty Duty cycle(1) Min Typ Max Unit 0.91 1 1.12 MHz 35 48.6 49.9 µA 54.4 1. These values are based on characterization. These values are not covered by test limits in production. 2. These values are based on simulation.
PAGE 1148
ATSAM4L8/L4/L2 42.7.9 80MHz RC Oscillator (RC80M) Characteristics Table 42-32. Internal 80MHz RC Oscillator Characteristics Symbol Parameter Conditions Min Typ Max Unit fOUT Output frequency (1) After calibration Note that RC80M is not available in PS1 60 80 100 MHz IRC80M Current consumption (2) tSTARTUP Startup time 330 (1) (2) Duty Duty cycle µA 0.57 1.72 3.2 µs 45 50 55 % 1. These values are based on characterization.
PAGE 1149
ATSAM4L8/L4/L2 1. These values are based on simulation. These values are not covered by test limits in production or characterization. Table 42-35. Flash Endurance and Data Retention (1) Symbol Parameter Conditions Min NFARRAY Array endurance (write/page) fCLK_AHB > 10MHz 100k NFFUSE General Purpose fuses endurance (write/bit) fCLK_AHB > 10MHz 10k tRET Data retention 1. Typ Max Unit cycles 15 years These values are based on simulation.
PAGE 1150
ATSAM4L8/L4/L2 42.9 Analog Characteristics 42.9.1 Voltage Regulator Characteristics Table 42-36. VREG Electrical Characteristics in Linear and Switching Modes Symbol Parameter DC output current (1) Power scaling mode 0 & 2 IOUT Min Typ Max Low power mode (WAIT) 2000 3600 5600 Ultra Low power mode (RETENTION) 100 180 300 Low power mode (WAIT) 4000 7000 10000 Ultra Low power mode (RETENTION) 200 350 600 Units µA DC output current(1) Power scaling mode 1 VVDDCORE 1.
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ATSAM4L8/L4/L2 Table 42-39. VREG Electrical Characteristics in Switching mode Symbol IOUT Parameter DC output current Conditions (1) Typ VVDDCORE > 1.65V (1) Max Units 55 mA Output DC load regulation Transient load regulation IOUT = 0 to 50mA, VVDDIN = 3V -136 -101 -82 mV Output DC regulation(1) IOUT = 50 mA, VVDDIN = 2V to 3.6V -20 38 99 mV VVDDIN = 2V, IOUT = 0 mA 97 186 546 VVDDIN > 2.2V, IOUT = 0 mA 97 111 147 82.7 88.
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ATSAM4L8/L4/L2 42.9.2 Power-on Reset 33 Characteristics Table 42-41. POR33 Characteristics (1) Symbol Parameter VPOT+ Voltage threshold on VVDDIN rising 1.25 1.55 VPOT- Voltage threshold on VVDDIN falling 0.95 1.30 1. Conditions Min Typ Max Units V These values are based on characterization. These values are not covered by test limits in production. VVDDIN Figure 42-4. POR33 Operating Principle VPOT+ VPOT- Reset Time 42.9.3 Brown Out Detectors Characteristics Table 42-42.
PAGE 1153
ATSAM4L8/L4/L2 1. These values are based on simulation. These values are not covered by test limits in production or characterization. The values in Table 42-43 describe the values of the BOD33.LEVEL in the flash User Page fuses. Table 42-43. BOD33.LEVEL Values BOD33.LEVEL Value Min Typ Max 16 2.08 20 2.18 24 2.33 28 2.48 32 2.62 36 2.77 40 2.92 44 3.06 48 3.21 Units V Table 42-44.
PAGE 1154
ATSAM4L8/L4/L2 42.9.4 Analog- to Digital Converter Characteristics Table 42-45. Operating conditions Symbol Parameter Conditions Min Temperature range Resolution Typ -40 (1) Max Sampling clock (3) fADC ADC clock frequency(3) TSAMPLEHOLD Sampling time(3) 12 Max Units +85 °C 12 (2) Differential modes, Gain=1X 5 300 Unipolar modes, Gain=1X 5 250 Differential modes 0.03 1.8 Unipolar modes 0.03 1.5 Differential modes 16.5 277 Unipolar modes 16.
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ATSAM4L8/L4/L2 Table 42-46. DC Characteristics Symbol VDDANA Parameter Supply voltage Conditions Max Units 1.6 3.6 V Differential mode 1.0 VDDANA -0.6 Unipolar and Window modes 1.0 1.0 (1) Reference range (2) Min Typ Using divide by two function (differential) VDDANA VDDANA +0.1 V 24 Cycles No gain compensation Reference buffer 5 µs Gain compensation Reference buffer 60 Cycles 0.5 kΩ 4.
PAGE 1156
ATSAM4L8/L4/L2 Table 42-47. Differential mode, gain=1 Offset error drift vs temperature(1) Conversion range (2) Vin-Vip -Vref mV/°K Vref V see Figure 42-5 ICMR(1) PSRR 0.04 (1) DC supply current (2) fvdd=1Hz, ext ADVREFP=3.0V VVDD=3.6V 100 fvdd=2MHz, ext ADVREFP=3.0V VVDD=3.6 50 VDDANA=3.6V, ADVREFP=3.0V 1.2 VDDANA=1.6V, ADVREFP=1.0V 0.6 dB mA 1. These values are based on simulation only. These values are not covered by test limits in production or characterization 2.
PAGE 1157
ATSAM4L8/L4/L2 Table 42-48. Unipolar mode, gain=1 PSRR (1) DC supply current (1) fvdd=1Hz, ext ADVREFP=3.0V VDDIO=3.6V 100 fvdd=2MHz, ext ADVREFP=3.0V VDDIO=3.6V 50 VDDANA=3.6V, ADVREFP=3.0V 1 1.8 VDDANA=1.6V, ADVREFP=1.0V 1 1.3 dB mA 1. These values are based on simulation. These values are not covered by test limits in production or characterization. 2.
PAGE 1158
ATSAM4L8/L4/L2 42.9.5 Digital to Analog Converter Characteristics Table 42-49. Operating conditions Symbol Parameter Analog Supply Voltage Digital Supply Voltage Resolution (1) (1) Conditions Min Typ Max Units on VDDANA 2.4 3 3.6 V on VDDCORE 1.62 1.8 1.
PAGE 1159
ATSAM4L8/L4/L2 Table 42-50. Analog Comparator Characteristics Symbol Parameter Hysteresis(1) Propagation delay(1) tSTARTUP IAC 1. Startup time (1) Channel current consumption (3) Conditions Min VACREFN =0.1V to VDDIO-0.1V, hysteresis = 1(2) Fast mode Typ Max Units 10 55 mV VACREFN =0.1V to VDDIO-0.1V, hysteresis = 1(2) Low power mode 10 68 mV VACREFN =0.1V to VDDIO-0.1V, hysteresis = 2(2) Fast mode 26 83 mV VACREFN =0.1V to VDDIO-0.
PAGE 1160
ATSAM4L8/L4/L2 42.9.7 Liquid Crystal Display Controler characteristics Table 42-51. Liquid Crystal Display Controler characteristics Symbol Parameter SEG Segment Terminal Pins 40 COM Common Terminal Pins 4 fFrame LCD Frame Frequency CFlying Flying Capacitor VLCD Conditions FCLKLCD Min Typ 31.25 512 100 Units Hz nF 3 LCD Regulated Voltages (1) CFG.FCST=0 BIAS2 CFlying = 100nF 100nF on VLCD, BIAS2 and BIAS1 pins 2*VLCD/3 V VLCD/3 BIAS1 1. Max These values are based on simulation.
PAGE 1161
ATSAM4L8/L4/L2 42.10 Timing Characteristics 42.10.1 RESET_N Timing Table 42-53. RESET_N Waveform Parameters (1) Symbol Parameter tRESET RESET_N minimum pulse length 1. Conditions Min 10 Max Units ns These values are based on simulation. These values are not covered by test limits in production. 42.10.2 42.10.2.1 USART in SPI Mode Timing Master mode Figure 42-7. USART in SPI Master Mode with (CPOL= CPHA= 0) or (CPOL= CPHA= 1) SPCK MISO USPI0 USPI1 MOSI USPI2 Figure 42-8.
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ATSAM4L8/L4/L2 Table 42-54. USART0 in SPI Mode Timing, Master Mode(1) Symbol Parameter USPI0 MISO setup time before SPCK rises USPI1 MISO hold time after SPCK rises USPI2 SPCK rising to MOSI delay USPI3 MISO setup time before SPCK falls USPI4 MISO hold time after SPCK falls USPI5 SPCK falling to MOSI delay Conditions Min 123.2 + VVDDIO from 3.0V to 3.6V, maximum external capacitor = 40pF Max Units tSAMPLE(2) 24.74 -tSAMPLE(2) 513.56 125.99 + ns tSAMPLE(2) 24.74 -tSAMPLE(2) 516.
PAGE 1163
ATSAM4L8/L4/L2 Maximum SPI Frequency, Master Output The maximum SPI master output frequency is given by the following formula: 1 f CLKSPI × 2 f SPCKMAX = MIN (f PINMAX,------------, -----------------------------) SPIn 9 Where SPIn is the MOSI delay, USPI2 or USPI5 depending on CPOL and NCPHA. f PINMAX is the maximum frequency of the SPI pins. refer to the I/O Pin Characteristics section for the maximum frequency of the pins. f CLKSPI is the maximum frequency of the CLK_SPI.
PAGE 1164
ATSAM4L8/L4/L2 Figure 42-10. USART in SPI Slave Mode with (CPOL= CPHA= 0) or (CPOL= CPHA= 1) SPCK MISO USPI9 MOSI USPI10 USPI11 Figure 42-11. USART in SPI Slave Mode, NPCS Timing USPI12 USPI13 USPI14 USPI15 SPCK, CPOL=0 SPCK, CPOL=1 NSS Table 42-58. USART0 in SPI mode Timing, Slave Mode(1) Symbol Parameter USPI6 SPCK falling to MISO delay Conditions Min Max 740.67 tSAMPLE(2) USPI7 MOSI setup time before SPCK rises 56.73 + tCLK_USART USPI8 MOSI hold time after SPCK rises 45.
PAGE 1165
ATSAM4L8/L4/L2 Table 42-59.
PAGE 1166
ATSAM4L8/L4/L2 Table 42-61. USART3 in SPI mode Timing, Slave Mode(1) Symbol Parameter Conditions USPI6 SPCK falling to MISO delay Min Max 593.9 tSAMPLE(2) + USPI7 MOSI setup time before SPCK rises 45.93 + tCLK_USART USPI8 MOSI hold time after SPCK rises 47.03 -( tSAMPLE(2) + tCLK_USART ) USPI9 SPCK rising to MISO delay VVDDIO from 3.0V to 3.6V, maximum external capacitor = 40pF 593.38 tSAMPLE(2) 45.
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ATSAM4L8/L4/L2 42.10.3 SPI Timing 42.10.3.1 Master mode Figure 42-12. SPI Master Mode with (CPOL= NCPHA= 0) or (CPOL= NCPHA= 1) SPCK MISO SPI0 SPI1 MOSI SPI2 Figure 42-13. SPI Master Mode with (CPOL= 0 and NCPHA= 1) or (CPOL= 1 and NCPHA= 0) SPCK MISO SPI3 SPI4 MOSI SPI5 Table 42-62.
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ATSAM4L8/L4/L2 The maximum SPI master output frequency is given by the following formula: 1 f SPCKMAX = MIN (f PINMAX,------------) SPIn Where SPIn is the MOSI delay, SPI2 or SPI5 depending on CPOL and NCPHA. f PINMAX is the maximum frequency of the SPI pins. refer to the I/O Pin Characteristics section for the maximum frequency of the pins.
PAGE 1169
ATSAM4L8/L4/L2 Figure 42-16. SPI Slave Mode, NPCS Timing SPI12 SPI13 SPI14 SPI15 SPCK, CPOL=0 SPCK, CPOL=1 NPCS Table 42-63. SPI Timing, Slave Mode(1) Symbol Parameter SPI6 SPCK falling to MISO delay SPI7 MOSI setup time before SPCK rises 2.1 SPI8 MOSI hold time after SPCK rises 7.
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ATSAM4L8/L4/L2 Where SPIn is the MISO delay, SPI6 or SPI9 depending on CPOL and NCPHA. t SETUP is the SPI master setup time. refer to the SPI master datasheet for t SETUP . f PINMAX is the maximum frequency of the SPI pins. refer to the I/O Pin Characteristics section for the maximum frequency of the pins. 42.10.4 TWIM/TWIS Timing Figure 42-64 shows the TWI-bus timing requirements and the compliance of the device with them.
PAGE 1171
ATSAM4L8/L4/L2 2. A device must internally provide a hold time of at least 300 ns for TWD with reference to the falling edge of TWCK. Notations: Cb = total capacitance of one bus line in pF tclkpb = period of TWI peripheral bus clock tprescaled = period of TWI internal prescaled clock (see chapters on TWIM and TWIS) The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW-TWI) of TWCK. 42.10.5 JTAG Timing Figure 42-17.
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ATSAM4L8/L4/L2 Table 42-65. JTAG Timings(1) Symbol Parameter JTAG0 TCK Low Half-period 21.8 JTAG1 TCK High Half-period 8.6 JTAG2 TCK Period 30.3 JTAG3 TDI, TMS Setup before TCK High JTAG4 TDI, TMS Hold after TCK High JTAG5 TDO Hold Time JTAG6 TCK Low to TDO Valid JTAG7 Boundary Scan Inputs Setup Time JTAG8 Boundary Scan Inputs Hold Time 6.9 JTAG9 Boundary Scan Outputs Hold Time 9.3 JTAG10 TCK to Boundary Scan Outputs Valid Note: Conditions VVDDIO from 3.0V to 3.
PAGE 1173
ATSAM4L8/L4/L2 Table 42-66. SWD Timings(1) Symbol Parameter Thigh SWDCLK High period Tlow SWDCLK Low period Tos SWDIO output skew to falling edge SWDCLK Tis Input Setup time required between SWDIO Tih Input Hold time required between SWDIO and rising edge SWDCLK Note: Conditions VVDDIO from 3.0V to 3.6V, maximum external capacitor = 40pF Min Max 10 500 000 10 500 000 -5 5 4 - 1 - Units ns 1. These values are based on simulation.
PAGE 1174
ATSAM4L8/L4/L2 43. Mechanical Characteristics 43.1 43.1.1 Thermal Considerations Thermal Data Table 43-1 summarizes the thermal resistance data depending on the package. Table 43-1. 43.1.2 Thermal Resistance Data Symbol Parameter Condition Package Typ θJA Junction-to-ambient thermal resistance Still Air TQFP100 48.1 θJC Junction-to-case thermal resistance TQFP100 13.3 θJA Junction-to-ambient thermal resistance VFBGA100 31.1 θJC Junction-to-case thermal resistance VFBGA100 6.
PAGE 1175
ATSAM4L8/L4/L2 43.2 Package Drawings Figure 43-1. VFBGA-100 package drawing Table 43-2. Device and Package Maximum Weight 120 Table 43-3. mg Package Characteristics Moisture Sensitivity Level Table 43-4.
PAGE 1176
ATSAM4L8/L4/L2 Figure 43-2. TQFP-100 Package Drawing Table 43-5. Device and Package Maximum Weight 500 Table 43-6. mg Package Characteristics Moisture Sensitivity Level Table 43-7.
PAGE 1177
ATSAM4L8/L4/L2 Figure 43-3. WLCSP64 SAM4LC4/2 Package Drawing Table 43-8. Device and Package Maximum Weight 14.8 Table 43-9. mg Package Characteristics Moisture Sensitivity Level MSL3 Table 43-10.
PAGE 1178
ATSAM4L8/L4/L2 Figure 43-4. WLCSP64 SAM4LS4/2 Package Drawing Table 43-11. Device and Package Maximum Weight 14.8 mg Table 43-12. Package Characteristics Moisture Sensitivity Level MSL3 Table 43-13.
PAGE 1179
ATSAM4L8/L4/L2 Figure 43-5. TQFP-64 Package Drawing Table 43-14. Device and Package Maximum Weight 300 mg Table 43-15. Package Characteristics Moisture Sensitivity Level MSL3 Table 43-16.
PAGE 1180
ATSAM4L8/L4/L2 Figure 43-6. QFN-64 Package Drawing Note: The exposed pad is not connected to anything internally, but should be soldered to ground to increase board level reliability. Table 43-17. Device and Package Maximum Weight 200 mg Table 43-18. Package Characteristics Moisture Sensitivity Level MSL3 Table 43-19.
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ATSAM4L8/L4/L2 Figure 43-7. TQFP-48 (ATSAM4LC4/2 and ATSAM4LS4/2 Only) Package Drawing Table 43-20. Device and Package Maximum Weight 140 mg Table 43-21. Package Characteristics Moisture Sensitivity Level MSL3 Table 43-22.
PAGE 1182
ATSAM4L8/L4/L2 Figure 43-8. QFN-48 Package Drawing for ATSAM4LC4/2 and ATSAM4LS4/2 Note: The exposed pad is not connected to anything internally, but should be soldered to ground to increase board level reliability. Table 43-23. Device and Package Maximum Weight 140 mg Table 43-24. Package Characteristics Moisture Sensitivity Level MSL3 Table 43-25.
PAGE 1183
ATSAM4L8/L4/L2 Figure 43-9. QFN-48 Package Drawing for ATSAM4LC8 and ATSAM4LS8 Note: The exposed pad is not connected to anything internally, but should be soldered to ground to increase board level reliability. Table 43-26. Device and Package Maximum Weight 140 mg Table 43-27. Package Characteristics Moisture Sensitivity Level MSL3 Table 43-28.
PAGE 1184
ATSAM4L8/L4/L2 43.3 Soldering Profile Table 43-29 gives the recommended soldering profile from J-STD-20. Table 43-29.
PAGE 1185
ATSAM4L8/L4/L2 44. Ordering Information Table 44-1.
PAGE 1186
ATSAM4L8/L4/L2 Table 44-3.
PAGE 1187
ATSAM4L8/L4/L2 Table 44-5.
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ATSAM4L8/L4/L2 45. Errata 45.1 45.1.1 ATSAM4L4 /2 Rev. B & ATSAM4L8 Rev. A General PS2 mode is not supported by Engineering Samples PS2 mode support is supported only by parts with calibration version higher than 0. Fix/Workaround The calibration version can be checked by reading a 32-bit word at address 0x0080020C. The calibration version bitfield is 4-bit wide and located from bit 4 to bit 7 in this word. Any value higher than 0 ensures that the part supports the PS2 mode 45.1.
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ATSAM4L8/L4/L2 Fix/Workaround Read the last received data, then perform a software reset by writing a one to the Software Reset bit in the Control Register (CR.SWRST). Disabling SPI has no effect on the SR.TDRE bit Disabling SPI has no effect on the SR.TDRE bit whereas the write data command is filtered when SPI is disabled. Writing to TDR when SPI is disabled will not clear SR.TDRE.
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ATSAM4L8/L4/L2 45.1.7 FLASHCALW Corrupted data in flash may happen after flash page write operations. After a flash page write operation, reading (data read or code fetch) in flash may fail. This may lead to an expecption or to others errors derived from this corrupted read access. Fix/Workaround Before any flash page write operation, each 64-bit doublewords write in the page buffer must preceded by a 64-bit doublewords write in the page buffer with 0xFFFFFFFF_FFFFFFFF content at any address in the page.
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ATSAM4L8/L4/L2 46. Datasheet Revision History Note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 46.1 46.2 46.3 46.4 Rev. A – 09/12 1. Initial revision. 1. Fixed ordering code 2. Changed BOD18CTRL and BOD33CTRL ACTION field from “Reserved” to ‘No action” 1. Fixed ball pitch for VFBGA100 package 2. Added VFBGA100 and WLCSP64 pinouts 3.
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ATSAM4L8/L4/L2 46.5 Rev. E – 07/13 1. Added ATSAM4L8 derivatives and WLCSP packages for ATSAM4L4/2 2. Added operating conditions details in Electrical Characteristics Chapter 3. Fixed “Supply Rise Rates and Order” 4. Added number of USART available in sub-series 5. Fixed IO line considerations for USB pins 6. Removed useless information about CPU local bus which is not implemented 7. Removed useless information about Modem support which is not implemented 8.
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ATSAM4L8/L4/L2 Table of Contents Summary.................................................................................................... 1 Features ..................................................................................................... 1 1 Description ............................................................................................... 3 2 Overview ................................................................................................... 5 3 4 5 6 7 2.
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ATSAM4L8/L4/L2 8 9 Debug and Test ...................................................................................... 61 8.1 Features ..........................................................................................................61 8.2 Overview ..........................................................................................................61 8.3 Block Diagram .................................................................................................62 8.
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ATSAM4L8/L4/L2 12.2 Overview ........................................................................................................160 12.3 Block Diagram ...............................................................................................161 12.4 I/O Lines Description .....................................................................................161 12.5 Product Dependencies ..................................................................................162 12.
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ATSAM4L8/L4/L2 15.5 User Interface ................................................................................................308 15.6 Module Configuration ....................................................................................316 16 Peripheral DMA Controller (PDCA) .................................................... 318 16.1 Features ........................................................................................................318 16.2 Overview ...........................
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ATSAM4L8/L4/L2 20 Watchdog Timer (WDT) ....................................................................... 481 20.1 Features ........................................................................................................481 20.2 Overview ........................................................................................................481 20.3 Block Diagram ...............................................................................................481 20.4 Product Dependencies ..
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ATSAM4L8/L4/L2 574 24.1 Features ........................................................................................................574 24.2 Overview ........................................................................................................574 24.3 Block Diagram ...............................................................................................575 24.4 I/O Lines Description ....................................................................................577 24.
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ATSAM4L8/L4/L2 27.7 Product Dependencies ..................................................................................706 27.8 Functional Description ...................................................................................708 27.9 User Interface ................................................................................................722 27.10 Module Configuration ....................................................................................
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ATSAM4L8/L4/L2 30.10 Module Configuration ....................................................................................843 31 Peripheral Event Controller (PEVC) ................................................... 844 31.1 Features ........................................................................................................844 31.2 Overview ........................................................................................................844 31.3 Block Diagram ..................
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ATSAM4L8/L4/L2 34.6 Functional Description ...................................................................................918 34.7 User Interface ................................................................................................927 34.8 Module Configuration ....................................................................................949 35 True Random Number Generator (TRNG) .......................................... 950 35.1 Features .........................................
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ATSAM4L8/L4/L2 38.6 Section 42. ”Electrical Characteristics” on page 1120Functional Description ..... 996 38.7 User Interface ..............................................................................................1004 38.8 Module Configuration ..................................................................................1031 39 LCD Controller (LCDCA) ................................................................... 1032 39.1 Features ......................................................
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ATSAM4L8/L4/L2 42.5 Power Consumption ....................................................................................1124 42.6 I/O Pin Characteristics .................................................................................1135 42.7 Oscillator Characteristics .............................................................................1142 42.8 Flash Characteristics ...................................................................................1148 42.9 Analog Characteristics ....
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