Datasheet

150
42023ES–SAM–07/2013
ATSAM4L8/L4/L2
Note: 1. These values are based on simulation. These values are not covered by test limits in production.
9.10.6 SWD Timing
Figure 9-18. SWD Interface Signals
Table 9-65. JTAG Timings
(1)
Symbol Parameter Conditions Min Max Units
JTAG0 TCK Low Half-period
V
VDDIO
from
3.0V to 3.6V,
maximum
external
capacitor =
40pF
21.8
ns
JTAG1 TCK High Half-period 8.6
JTAG2 TCK Period 30.3
JTAG3 TDI, TMS Setup before TCK High 2.0
JTAG4 TDI, TMS Hold after TCK High 2.3
JTAG5 TDO Hold Time 9.5
JTAG6 TCK Low to TDO Valid 21.8
JTAG7 Boundary Scan Inputs Setup Time 0.6
JTAG8 Boundary Scan Inputs Hold Time 6.9
JTAG9 Boundary Scan Outputs Hold Time 9.3
JTAG10 TCK to Boundary Scan Outputs Valid 32.2
Stop Park Tri State
AcknowledgeTri State Tri State
Parity StartData Data
Stop Park Tri State
AcknowledgeTri State
Start
Read Cycle
Write Cycle
Tos
Thigh
Tlow
Tis
Data Data Parity Tri State
Tih
From debugger to
SWDIO pin
From debugger to
SWDCLK pin
SWDIO pin to
debugger
From debugger to
SWDIO pin
From debugger to
SWDCLK pin
SWDIO pin to
debugger