Datasheet

142
42023ES–SAM–07/2013
ATSAM4L8/L4/L2
Figure 9-10. USART in SPI Slave Mode with (CPOL= CPHA= 0) or (CPOL= CPHA= 1)
Figure 9-11. USART in SPI Slave Mode, NPCS Timing
USPI10 USPI11
MISO
SPCK
MOSI
USPI9
USPI14
USPI12
USPI15
USPI13
NSS
SPCK, CPOL=0
SPCK, CPOL=1
Table 9-58. USART0 in SPI mode Timing, Slave Mode
(1)
Symbol Parameter Conditions Min Max Units
USPI6 SPCK falling to MISO delay
V
VDDIO
from
3.0V to 3.6V,
maximum
external
capacitor =
40pF
740.67
ns
USPI7 MOSI setup time before SPCK rises
56.73 + t
SAMPLE
(2)
+
t
CLK_USART
USPI8 MOSI hold time after SPCK rises
45.18 -( t
SAMPLE
(2)
+
t
CLK_USART )
USPI9 SPCK rising to MISO delay 670.18
USPI10 MOSI setup time before SPCK falls
56.73 +( t
SAMPLE
(2)
+
t
CLK_USART )
USPI11 MOSI hold time after SPCK falls
45.18 -( t
SAMPLE
(2)
+
t
CLK_USART )
USPI12 NSS setup time before SPCK rises 688.71
USPI13 NSS hold time after SPCK falls -2.25
USPI14 NSS setup time before SPCK falls 688.71
USPI15 NSS hold time after SPCK rises -2.25