Datasheet

123
42023ES–SAM–07/2013
ATSAM4L8/L4/L2
9.7.3 Phase Locked Loop (PLL) Characteristics
9.7.4 Digital Frequency Locked Loop (DFLL) Characteristics
Table 9-26. Phase Locked Loop Characteristics
Symbol Parameter Conditions Min Typ Max Unit
f
OUT
Output frequency
(1)
1. These values are based on simulation. These values are not covered by test limits in production or characterization.
PLL is not availabe in PS1 48 240
MHz
f
IN
Input frequency
(1)
416
I
PLL
Current consumption
(1)
fout=80MHz 200
µA
fout=240MHz 500
t
STARTUP
Startup time, from enabling
the PLL until the PLL is
locked
(1)
Wide Bandwidth mode disabled 8
µs
Wide Bandwidth mode enabled 30
Table 9-27. Digital Frequency Locked Loop Characteristics
Symbol Parameter Conditions Min Typ Max Unit
f
OUT
Output frequency
(1)
DFLL is not availabe in PS1 20 150 MHz
f
REF
Reference frequency
(1)
8 150 kHz
Accuracy
(1)
FINE lock, f
REF
= 32kHz, SSG disabled
(2)
0.1 0.5
%
ACCURATE lock, f
REF
= 32kHz, dither clk
RCSYS/2, SSG disabled
(2)
0.06 0.5
FINE lock, f
REF
= 8-150kHz, SSG
disabled
(2)
0.2 1
ACCURATE lock, f
REF
= 8-150kHz,
dither clk RCSYS/2, SSG disabled
(2)
0.1 1
I
DFLL
Power consumption
(1)
RANGE 0 96 to 220MHz
COARSE=0, FINE=0, DIV=0
430 509 545
µA
RANGE 0 96 to 220MHz
COARSE=31, FINE=255, DIV=0
1545 1858 1919
RANGE 1 50 to 110MHz
COARSE=0, FINE=0, DIV=0
218 271 308
RANGE 1 50 to 110MHz
COARSE=31, FINE=255, DIV=0
704 827 862
RANGE 2 25 to 55MHz
COARSE=0, FINE=0, DIV=1
140 187 226
RANGE 2 25 to 55MHz
COARSE=31, FINE=255, DIV=1
365 441 477
RANGE 3 20 to 30MHz
COARSE=0, FINE=0, DIV=1
122 174 219
RANGE 3 20 to 30MHz
COARSE=31, FINE=255, DIV=1
288 354 391