Datasheet

3
SAM4E [SUMMARY DATASHEET]
11157CS–ATARM–25-Jul-13
 Real-time Event Management
 Cryptography
 AES 256-bit Key Algorithm compliant with FIPS Publication 197
 Analog
 AFE (Analog Front End): 2x16-bit ADC, up to 24-channels, Differential Input Mode, Programmable Gain
Stage, Auto Calibration and Automatic Offset Correction
 One 2-channel 12-bit 1 Msps DAC
 One Analog Comparator with Flexible Input Selection, Selectable Input Hysteresis
 I/O
 Up to 117 I/O Lines with External Interrupt Capability (Edge or Level Sensitivity), Debouncing, Glitch
Filtering and On-die Series Resistor Termination
 Bidirectional Pad, Analog I/O, Programmable Pull-up/Pull-down
 Five 32-bit Parallel Input/Output Controllers, Peripheral DMA Assisted Parallel Capture Mode
 Packages
 144-ball LFBGA, 10x10 mm, pitch 0.8 mm
 100-ball TFBGA, 9x9 mm, pitch 0.8 mm
 144-lead LQFP, 20x20 mm, pitch 0.5 mm
 100-lead LQFP, 14x14 mm, pitch 0.5 mm
Note: 1. 120 MHz: -40/+105°C, VDDCORE = 1.2V or using internal voltage regulator