Datasheet

99
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
 Rm must not be SP and must not be PC
 Rt can be SP only for word loads and word stores
 Rt can be PC only for word loads.
When Rt is PC in a word load instruction:
 Bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this halfword-aligned
address
 If the instruction is conditional, it must be the last instruction in the IT block.
Condition Flags
These instructions do not change the flags.
Examples
STR R0, [R5, R1] ; Store value of R0 into an address equal to
; sum of R5 and R1
LDRSB R0, [R5, R1, LSL #1] ; Read byte value from an address equal to
; sum of R5 and two times R1, sign extended it
; to a word value and put it in R0
STR R0, [R1, R2, LSL #2] ; Stores R0 to an address equal to sum of R1
; and four times R2