Datasheet

SAM4E [DATASHEET]

Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14

984

39.7 Timer Counter (TC) User Interface

Notes: 1. Channel index ranges from 0 to 2.

2. Read-only if WAVE = 0

Table 39-5. Register Mapping

Offset

(1)

0x00 + channel * 0x40 + 0x00 Channel Control Register TC_CCR Write-only –

0x00 + channel * 0x40 + 0x04 Channel Mode Register TC_CMR Read/Write 0

0x00 + channel * 0x40 + 0x08 Stepper Motor Mode Register TC_SMMR Read/Write 0

0x00 + channel * 0x40 + 0x0C Register AB TC_RAB Read-only 0

0x00 + channel * 0x40 + 0x10 Counter Value TC_CV Read-only 0

0x00 + channel * 0x40 + 0x14 Register A TC_RA Read/Write

(2)

0x00 + channel * 0x40 + 0x18 Register B TC_RB Read/Write

(2)

0x00 + channel * 0x40 + 0x1C Register C TC_RC Read/Write 0

0x00 + channel * 0x40 + 0x20 Status Register TC_SR Read-only 0

0x00 + channel * 0x40 + 0x24 Interrupt Enable Register TC_IER Write-only –

0x00 + channel * 0x40 + 0x28 Interrupt Disable Register TC_IDR Write-only –

0x00 + channel * 0x40 + 0x2C Interrupt Mask Register TC_IMR Read-only 0

0x00 + channel * 0x40 + 0x30 Extended Mode Register TC_EMR Read/Write 0

0xC0 Block Control Register TC_BCR Write-only –

0xC4 Block Mode Register TC_BMR Read/Write 0

0xC8 QDEC Interrupt Enable Register TC_QIER Write-only –

0xCC QDEC Interrupt Disable Register TC_QIDR Write-only –

0xD0 QDEC Interrupt Mask Register TC_QIMR Read-only 0

0xD4 QDEC Interrupt Status Register TC_QISR Read-only 0

0xD8 Fault Mode Register TC_FMR Read/Write 0

0xE4 Write Protection Mode Register TC_WPMR Read/Write 0

0xE8–0xFC Reserved – – –

0x100–0x1A4 Reserved for PDC Registers – – –