Datasheet

SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
960
39.5.2 Power Management
The TC is clocked through the Power Management Controller (PMC), thus the programmer must first configure the
PMC to enable the Timer Counter clock.
39.5.3 Interrupt
The TC has an interrupt line connected to the Interrupt Controller (IC). Handling the TC interrupt requires
programming the IC before configuring the TC.
39.5.4 Synchronization Inputs from PWM
The TC has trigger/capture inputs internally connected to the PWM. Refer to Section 39.6.14 “Synchronization with
PWM” and to the product Pulse Width Modulation (PWM) implementation.
39.5.5 Fault Output
The TC has the FAULT output internally connected to the fault input of PWM. Refer to Section 39.6.19 “Fault
Mode” and to the product Pulse Width Modulation (PWM) implementation.
39.6 Functional Description
39.6.1 TC Description
The nine channels of the Timer Counter are independent and identical in operation except when quadrature
decoder is enabled. The registers for channel programming are listed in Table 39-5 “Register Mapping”.
39.6.2 32-bit Counter
Each channel is organized around a 32-bit counter. The value of the counter is incremented at each positive edge
of the selected clock. When the counter has reached the value 2
32
-1 and passes to zero, an overflow occurs and
the COVFS bit in the TC Status Register (TC_SR) is set.
The current value of the counter is accessible in real time by reading the TC Counter Value Register (TC_CV). The
counter can be reset by a trigger. In this case, the counter value passes to zero on the next valid edge of the
selected clock.
TC1 TIOB4 PC27 B
TC1 TIOB5 PC30 B
TC2 TCLK6 PC7 B
TC2 TCLK7 PC10 B
TC2 TCLK8 PC14 B
TC2 TIOA6 PC5 B
TC2 TIOA7 PC8 B
TC2 TIOA8 PC11 B
TC2 TIOB6 PC6 B
TC2 TIOB7 PC9 B
TC2 TIOB8 PC12 B
Table 39-4. I/O Lines