Datasheet

927
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
38.8.3 USART Mode Register
Name: US_MR
Address: 0x400A0004 (0), 0x400A4004 (1)
Access: Read/Write
This register can only be written if the WPEN bit is cleared in “USART Write Protection Mode Register” on page 955.
For SPI configuration, see “USART Mode Register (SPI_MODE)” on page 930.
 USART_MODE: USART Mode of Operation
The PDC transfers are supported in all USART modes of operation.
 USCLKS: Clock Selection
31 30 29 28 27 26 25 24
ONEBIT MODSYNC MAN FILTER – MAX_ITERATION
23 22 21 20 19 18 17 16
INVDATA VAR_SYNC DSNACK INACK OVER CLKO MODE9 MSBF
15 14 13 12 11 10 9 8
CHMODE NBSTOP PAR SYNC
76543210
CHRL USCLKS USART_MODE
Value Name Description
0x0 NORMAL Normal mode
0x1 RS485 RS485
0x2 HW_HANDSHAKING Hardware Handshaking
0x3 MODEM Modem
0x4 IS07816_T_0 IS07816 Protocol: T = 0
0x6 IS07816_T_1 IS07816 Protocol: T = 1
0x8 IRDA IrDA
0xE SPI_MASTER SPI master
0xF SPI_SLAVE SPI Slave
Value Name Description
0 MCK Peripheral clock is selected
1 DIV Peripheral clock divided (DIV=8) is selected
3 SCK Serial clock SCK is selected