Datasheet

861
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
36.8.9 TWI Interrupt Mask Register
Name: TWI_IMR
Address: 0x400A802C (0), 0x400AC02C (1)
Access: Read-only
Reset: 0x00000000
The following configuration values are valid for all listed bit names of this register:
0: The corresponding interrupt is disabled.
1: The corresponding interrupt is enabled.
 TXCOMP: Transmission Completed Interrupt Mask
 RXRDY: Receive Holding Register Ready Interrupt Mask
 TXRDY: Transmit Holding Register Ready Interrupt Mask
 SVACC: Slave Access Interrupt Mask
 GACC: General Call Access Interrupt Mask
 OVRE: Overrun Error Interrupt Mask
 NACK: Not Acknowledge Interrupt Mask
 ARBLST: Arbitration Lost Interrupt Mask
 SCL_WS: Clock Wait State Interrupt Mask
 EOSACC: End Of Slave Access Interrupt Mask
 ENDRX: End of Receive Buffer Interrupt Mask
 ENDTX: End of Transmit Buffer Interrupt Mask
 RXBUFF: Receive Buffer Full Interrupt Mask
 TXBUFE: Transmit Buffer Empty Interrupt Mask
31 30 29 28 27 26 25 24
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23 22 21 20 19 18 17 16
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15 14 13 12 11 10 9 8
TXBUFE RXBUFF ENDTX ENDRX EOSACC SCL_WS ARBLST NACK
76543210
–OVREGACC SVACC – TXRDY RXRDY TXCOMP