Datasheet

SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
856
36.8.6 TWI Status Register
Name: TWI_SR
Address: 0x400A8020 (0), 0x400AC020 (1)
Access: Read-only
Reset: 0x0000F009
 TXCOMP: Transmission Completed (automatically set / reset)
TXCOMP used in Master mode:
0: During the length of the current frame.
1: When both holding register and internal shifter are empty and STOP condition has been sent.
TXCOMP behavior in Master mode can be seen in Figure 36-8 on page 828 and in Figure 36-10 on page 829.
TXCOMP used in Slave mode
:
0: As soon as a Start is detected.
1: After a Stop or a Repeated Start + an address different from SADR is detected.
TXCOMP behavior in Slave mode can be seen in Figure 36-29 on page 845, Figure 36-30 on page 846, Figure 36-31 on
page 846 and Figure 36-32 on page 847.
 RXRDY: Receive Holding Register Ready (automatically set / reset)
0: No character has been received since the last TWI_RHR read operation.
1: A byte has been received in the TWI_RHR since the last read.
RXRDY behavior in Master mode can be seen in Figure 36-10 on page 829.
RXRDY behavior in Slave mode can be seen in Figure 36-27 on page 844, Figure 36-30 on page 846, Figure 36-31 on
page 846 and Figure 36-32 on page 847.
 TXRDY: Transmit Holding Register Ready (automatically set / reset)
TXRDY used in Master mode:
0: The transmit holding register has not been transferred into internal shifter. Set to 0 when writing into TWI_THR.
1: As soon as a data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at
the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI).
TXRDY behavior in Master mode can be seen in Section 36.7.3.4 “Master Transmitter Mode”.
TXRDY used in Slave mode
:
0: As soon as data is written in the TWI_THR, until this data has been transmitted and acknowledged (ACK or NACK).
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TXBUFE RXBUFF ENDTX ENDRX EOSACC SCLWS ARBLST NACK
76543210
–OVREGACC SVACC SVREAD TXRDY RXRDY TXCOMP