Datasheet

SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
818
 BITS: Bits Per Transfer
(See the note below the register bitmap.)
The BITS field determines the number of data bits transferred. Reserved values should not be used.
 SCBR: Serial Clock Baud Rate
In Master mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the peripheral clock. The
Baud rate is selected by writing a value from1 to 255 in the SCBR field. The following equations determine the SPCK baud
rate:
Do not program the SCBR field to 0. Triggering a transfer while SCBR is at 0 can lead to unpredictable results.
At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer.
Note: If one of the SCBR fields in SPI_CSRx is set to 1, the other SCBR fields in SPI_CSRx must be set to 1 as well, if they are used to
process transfers. If they are not used to transfer data, they can be set at any value.
 DLYBS: Delay Before SPCK
This field defines the delay from NPCS falling edge (activation) to the first valid SPCK transition.
When DLYBS equals zero, the NPCS valid to SPCK transition is half the SPCK clock period.
Otherwise, the following equations determine the delay:
 DLYBCT: Delay Between Consecutive Transfers
This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select.
The delay is always inserted after each transfer and before removing the chip select if needed.
Value Name Description
0 8_BIT 8 bits for transfer
1 9_BIT 9 bits for transfer
2 10_BIT 10 bits for transfer
3 11_BIT 11 bits for transfer
4 12_BIT 12 bits for transfer
5 13_BIT 13 bits for transfer
6 14_BIT 14 bits for transfer
7 15_BIT 15 bits for transfer
8 16_BIT 16 bits for transfer
9– Reserved
10 – Reserved
11 – Reserved
12 – Reserved
13 – Reserved
14 – Reserved
15 – Reserved
SPCK Baudrate
f
peripheral clock
SCBR
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Delay Before SPCK
DLYBS
f
peripheral clock
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