Datasheet

785
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
34.6.53 PIO Parallel Capture Interrupt Mask Register
Name: PIO_PCIMR
Address: 0x400E0F5C (PIOA), 0x400E115C (PIOB), 0x400E135C (PIOC), 0x400E155C (PIOD), 0x400E175C
(PIOE)
Access: Read-only
The following configuration values are valid for all listed bit names of this register:
0: Corresponding interrupt is not enabled.
1: Corresponding interrupt is enabled.
 DRDY: Parallel Capture Mode Data Ready Interrupt Mask
 OVRE: Parallel Capture Mode Overrun Error Interrupt Mask
 ENDRX: End of Reception Transfer Interrupt Mask
 RXBUFF: Reception Buffer Full Interrupt Mask
31 302928 27 26 25 24
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23 22 21 20 19 18 17 16
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15 14 13 12 11 10 9 8
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76543 210
––––RXBUFFENDRX OVRE
DRDY