Datasheet

SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
712
34.2 Embedded Characteristics
 Up to 32 Programmable I/O Lines
 Fully Programmable through Set/Clear Registers
 Multiplexing of Four Peripheral Functions per I/O Line
 For each I/O Line (Whether Assigned to a Peripheral or Used as General Purpose I/O)
̶ Input Change Interrupt
̶ Programmable Glitch Filter
̶ Programmable Debouncing Filter
̶ Multi-drive Option Enables Driving in Open Drain
̶ Programmable Pull-Up on Each I/O Line
̶ Pin Data Status Register, Supplies Visibility of the Level on the Pin at Any Time
̶ Additional Interrupt Modes on a Programmable Event: Rising Edge, Falling Edge, Low-Level or High-
Level
̶ Lock of the Configuration by the Connected Peripheral
 Synchronous Output, Provides Set and Clear of Several I/O Lines in a Single Write
 Register Write Protection
 Programmable Schmitt Trigger Inputs
 Programmable I/O Delay
 Parallel Capture Mode
̶ Can Be Used to Interface a CMOS Digital Image Sensor, an ADC, etc.
̶ One Clock, 8-bit Parallel Data and Two Data Enable on I/O Lines
̶ Data Can be Sampled Every Other Time (For Chrominance Sampling Only)
̶ Supports Connection of One Peripheral DMA Controller Channel (PDC) Which Offers Buffer
Reception Without Processor Intervention