Datasheet

SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
594
30.15 Clock Switching Details
30.15.1 Master Clock Switching Timings
Table 30-1 and give the worst case timings required for the master clock to switch from one selected clock to
another one. This is in the event that the prescaler is de-activated. When the prescaler is activated, an additional
time of 64 clock cycles of the newly selected clock has to be added.
Notes: 1. PLL designates the PLLA .
2. PLLCOUNT designates PLLACOUNT .
Table 30-1. Clock Switching Timings (Worst Case)
Fro
m Main Clock SLCK PLL Clock
To
Main
Clock
–
4 x SLCK +
2.5 x Main Clock
3 x PLL Clock +
4 x SLCK +
1 x Main Clock
SLCK
0.5 x Main Clock +
4.5 x SLCK
–
3 x PLL Clock +
5 x SLCK
PLL Clock
0.5 x Main Clock +
4 x SLCK +
PLLCOUNT x SLCK +
2.5 x PLLx Clock
2.5 x PLL Clock +
5 x SLCK +
PLLCOUNT x SLCK
2.5 x PLL Clock +
4 x SLCK +
PLLCOUNT x SLCK