Datasheet

509
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
27.3 Peripheral DMA Controller Connections
The Peripheral DMA Controller is composed of two PDCs (PDC0 and PDC1) which handle the data transfer
between peripherals and memory and receive triggers from the peripherals listed in tables that follow.
27.3.1 Peripheral DMA Controller 0 (PDC0)
The Peripheral DMA Controller 0 handles transfer requests from the channel according to the following priorities
(Channel 0 is high priority):
Table 27-1. Peripheral DMA Controller (PDC0)
Instance Name Channel T/R Channel Number
TC5 Receive 23
TC4 Receive 22
TC3 Receive 21
TC2 Receive 20
TC1 Receive 19
TC0 Receive 18
TWI1 Transmit 17
TWI0 Transmit 16
UART0 Transmit 15
USART0 Transmit 14
USART1 Transmit 13
DACC Transmit 12
SPI Transmit 11
HSMCI Transmit 10
PIOA Receive 9
TWI1 Receive 8
TWI0 Receive 7
UART0 Receive 6
USART0 Receive 5
USART1 Receive 4
AFEC1 Receive 3
AFEC0 Receive 2
SPI Receive 1
HSMCI Receive 0