Datasheet

SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
502
26.8.17 DMAC Channel x [x = 0..3] Control B Register
Name: DMAC_CTRLBx [x = 0..3]
Address: 0x400C004C [0], 0x400C0074 [1], 0x400C009C [2], 0x400C00C4 [3]
Access: Read-write
Reset: 0x00000000
This register can only be written if the WPEN bit is cleared in “DMAC Write Protect Mode Register” .
 SRC_DSCR: Source Address Descriptor
0 (FETCH_FROM_MEM): Source address is updated when the descriptor is fetched from the memory.
1 (FETCH_DISABLE): Buffer Descriptor Fetch operation is disabled for the source.
 DST_DSCR: Destination Address Descriptor
0 (FETCH_FROM_MEM): Destination address is updated when the descriptor is fetched from the memory.
1 (FETCH_DISABLE): Buffer Descriptor Fetch operation is disabled for the destination.
 FC: Flow Control
This field defines which device controls the size of the buffer transfer, also referred to as the Flow Controller.
 SRC_INCR: Incrementing, Decrementing or Fixed Address for the Source
31 30 29 28 27 26 25 24
– IEN DST_INCR – – SRC_INCR
23 22 21 20 19 18 17 16
– FC DST_DSCR – – – SRC_DSCR
15 14 13 12 11 10 9 8
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Value Name Description
00 MEM2MEM_DMA_FC Memory-to-Memory Transfer DMAC is flow controller
01 MEM2PER_DMA_FC Memory-to-Peripheral Transfer DMAC is flow controller
10 PER2MEM_DMA_FC Peripheral-to-Memory Transfer DMAC is flow controller
11 PER2PER_DMA_FC Peripheral-to-Peripheral Transfer DMAC is flow controller
Value Name Description
00 INCREMENTING The source address is incremented
01 DECREMENTING The source address is decremented
10 FIXED The source address remains unchanged