Datasheet

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SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
25.2.3 Master to Slave Access
All the Masters can normally access all the Slaves. However, some paths do not make sense, for example
allowing access from the Cortex-M4 S Bus to the Internal SRAM. Thus, these paths are forbidden or simply not
wired, and shown as “
–” in Table 25-2.
Slave 3 Peripheral Bridge 0
Slave 4 Peripheral Bridge 1
Slave 5 External Bus Interface (EBI)
Table 25-1. List of Bus Matrix Slaves (Continued)
Table 25-2. Master to Slave Access
Slaves Masters
0 1 2 3 4 5 6
Cortex-M4
I/D Bus
Cortex-M4 S
Bus PDC1 DMAC Reserved EMAC
0 Internal SRAM – X X X X – X
1 Internal ROM X – X X X – X
2 Internal Flash X – – – – – –
3 Peripheral Bridge 0 – X X – X – –
4 Peripheral Bridge 1 – X – X X – –
5
External Bus Interface
(EBI)
–XXXX–X