Datasheet

SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
430
23.5 Cortex M Cache Controller (CMCC) User Interface
Table 23-1. Register Mapping
Offset Register Name Access Reset
0x00 Cache Type Register CMCC_TYPE Read-only –
0x04 Cache Configuration Register CMCC_CFG Read-write 0x00000000
0x08 Cache Control Register CMCC_CTRL Write-only –
0x0C Cache Status Register CMCC_SR Read-only 0x00000001
0x10 - 0x1C Reserved – – –
0x20 Cache Maintenance Register 0 CMCC_MAINT0 Write-only –
0x24 Cache Maintenance Register 1 CMCC_MAINT1 Write-only –
0x28 Cache Monitor Configuration Register CMCC_MCFG Read-write 0x00000000
0x2C Cache Monitor Enable Register CMCC_MEN Read-write 0x00000000
0x30 Cache Monitor Control Register CMCC_MCTRL Write-only –
0x34 Cache Monitor Status Register CMCC_MSR Read-only 0x00000000
0x38 - 0xFC Reserved – – –