Datasheet

265
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
The table below shows the encodings for the TEX, C, B, and S access permission bits.
Note: 1. The MPU ignores the value of this bit.
Table 12-38 shows the cache policy for memory attribute encodings with a TEX value is in the range 4–7.
Table 12-37. TEX, C, B, and S Encoding
TEX C B S Memory Type Shareability Other Attributes
b000
0
0 x
(1)
Strongly-ordered Shareable –
1 x
(1)
Device Shareable –
1
0
0
Normal
Not
shareable
Outer and inner write-through. No
write allocate.
1 Shareable
1
0
Normal
Not
shareable
Outer and inner write-back. No write
allocate.
1 Shareable
b001
0
0
0
Normal
Not
shareable
Outer and inner noncacheable.
1 Shareable
1 x
(1)
Reserved encoding –
1
0 x
(1)
Implementation defined
attributes.
–
1
0
Normal
Not
shareable
Outer and inner write-back. Write and
read allocate.
1 Shareable
b010
0
0 x
(1)
Device
Not
shareable
Nonshared Device.
1 x
(1)
Reserved encoding –
1x
(1)
x
(1)
Reserved encoding –
b1BB A A
0
Normal
Not
shareable
Cached memory BB = outer policy,
AA = inner policy.
1 Shareable
Table 12-38. Cache Policy for Memory Attribute Encoding
Encoding, AA or BB Corresponding Cache Policy
00 Non-cacheable
01 Write back, write and read allocate
10 Write through, no write allocate
11 Write back, no write allocate