Datasheet

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SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
 INVPC: Invalid PC Load Usage Fault
This is part of “UFSR: Usage Fault Status Subregister” . It is caused by an invalid PC load by EXC_RETURN:
0: No invalid PC load usage fault.
1: The processor has attempted an illegal load of EXC_RETURN to the PC, as a result of an invalid context, or an invalid
EXC_RETURN value.
When this bit is set to 1, the PC value stacked for the exception return points to the instruction that tried to perform the ille-
gal load of the PC.
 NOCP: No Coprocessor Usage Fault
This is part of “UFSR: Usage Fault Status Subregister” . The processor does not support coprocessor instructions:
0: No usage fault caused by attempting to access a coprocessor.
1: The processor has attempted to access a coprocessor.
 UNALIGNED: Unaligned Access Usage Fault
This is part of “UFSR: Usage Fault Status Subregister” .
0: No unaligned access fault, or unaligned access trapping not enabled.
1: The processor has made an unaligned memory access.
Enable trapping of unaligned accesses by setting the UNALIGN_TRP bit in the SCB_CCR to 1. See “Configuration and
Control Register” . Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of the setting of
UNALIGN_TRP.
 DIVBYZERO: Divide by Zero Usage Fault
This is part of “UFSR: Usage Fault Status Subregister” .
0: No divide by zero fault, or divide by zero trapping not enabled.
1: The processor has executed an SDIV or UDIV instruction with a divisor of 0.
When the processor sets this bit to 1, the PC value stacked for the exception return points to the instruction that performed
the divide by zero. Enable trapping of divide by zero by setting the DIV_0_TRP bit in the SCB_CCR to 1. See “Configura-
tion and Control Register” .