Datasheet

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SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
12.9.1.8 System Handler Priority Registers
The SCB_SHPR1–SCB_SHPR3 registers set the priority level, 0 to 15 of the exception handlers that have configurable pri-
ority. They are byte-accessible.
The system fault handlers and the priority field and register for each handler are:
Each PRI_N field is 8 bits wide, but the processor implements only bits [7:4] of each field, and bits [3:0] read as zero and
ignore writes.
Table 12-34. System Fault Handler Priority Fields
Handler Field Register Description
Memory management fault (MemManage) PRI_4
System Handler Priority Register 1Bus fault (BusFault) PRI_5
Usage fault (UsageFault) PRI_6
SVCall PRI_11 System Handler Priority Register 2
PendSV PRI_14
System Handler Priority Register 3
SysTick PRI_15