Datasheet

SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
224
12.8.3.1 Interrupt Set-enable Registers
Name: NVIC_ISERx [x=0..7]
Access: Read/Write
Reset: 0x000000000
These registers enable interrupts and show which interrupts are enabled.
 SETENA: Interrupt Set-enable
Write:
0: No effect.
1: Enables the interrupt.
Read:
0: Interrupt disabled.
1: Interrupt enabled.
Notes: 1. If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority.
2. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, the NVIC never activates
the interrupt, regardless of its priority.
31 30 29 28 27 26 25 24
SETENA
23 22 21 20 19 18 17 16
SETENA
15 14 13 12 11 10 9 8
SETENA
76543210
SETENA