Datasheet

SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
192
12.6.11.11 VLDR
Loads a single extension register from memory
Syntax
VLDR{cond}{.64} Dd, [Rn{#imm}]
VLDR{cond}{.64} Dd, label
VLDR{cond}{.64} Dd, [PC, #imm}]
VLDR{cond}{.32} Sd, [Rn {, #imm}]
VLDR{cond}{.32} Sd, label
VLDR{cond}{.32} Sd, [PC, #imm]
where:
cond is an optional condition code, see “Conditional Execution” .
64, 32 are the optional data size specifiers.
Dd is the destination register for a doubleword load.
Sd is the destination register for a singleword load.
Rn is the base register. The SP can be used.
imm is the + or - immediate offset used to form the address.
Permitted address values are multiples of 4 in the range 0 to 1020.
label is the label of the literal data item to be loaded.
Operation
This instruction:
 Loads a single extension register from memory, using a base address from an ARM core register, with an
optional offset.
Restrictions
There are no restrictions.
Condition Flags
These instructions do not change the flags.